diff --git a/core/lpc/core.py b/core/lpc/core.py
index 4fcd04d..63c5938 100644
--- a/core/lpc/core.py
+++ b/core/lpc/core.py
@@ -3,13 +3,15 @@ import os
 from migen import *
 
 from litex.soc.interconnect import wishbone
+from litex.soc.interconnect.csr import *
 
 this_dir = os.path.dirname(os.path.realpath(__file__))
 deps_dir = os.path.join(os.path.dirname(this_dir), "deps")
 
 
-class LPCBone(Module):
+class LPCBone(Module, AutoCSR):
     def __init__(self, platform, pads):
+        self.hold = CSRStorage(32, reset=1)
         self.bus = wishbone.Interface()
 
         self.submodules.lpc2wb = lpc2wishbone(pads)
@@ -20,6 +22,8 @@ class LPCBone(Module):
         # crossing.
         self.comb += [
             self.wb_async.bus_sys.connect(self.bus),
+            self.bus.cyc.eq(self.wb_async.bus_sys.cyc & ~self.hold.storage[0]),
+            self.bus.stb.eq(self.wb_async.bus_sys.stb & ~self.hold.storage[0]),
             self.lpc2wb.bus.connect(self.wb_async.bus_lpc)
         ]