#!/usr/bin/env python3

from litex import RemoteClient

wb = RemoteClient()
wb.open()

def mem_dump(base, length):
    for addr in range(base, base + length, 4):
        if (addr%16 == 0):
            if addr != base:
                print("")
            print("0x{:08x}".format(addr), end="  ")
        data = wb.read(addr)
        for i in reversed(range(4)):
            print("{:02x}".format((data >> (8*i)) & 0xff), end=" ")
    print("")

def mem_write(base, datas):
    for n, addr in enumerate(range(base, base + 4*len(datas), 4)):
        if (addr%16 == 0):
            if addr != base:
                print("")
            print("0x{:08x}".format(addr), end="  ")
        data = datas[n]
        for i in reversed(range(4)):
            print("{:02x}".format((data >> (8*i)) & 0xff), end=" ")
        wb.write(addr, data)
    print("")

import time

DFII_CONTROL_SEL = 0x01
DFII_CONTROL_CKE = 0x02
DFII_CONTROL_ODT = 0x04
DFII_CONTROL_RESET_N = 0x08
DFII_COMMAND_CS = 0x01
DFII_COMMAND_WE = 0x02
DFII_COMMAND_CAS = 0x04
DFII_COMMAND_RAS = 0x08
DFII_COMMAND_WRDATA = 0x10
DFII_COMMAND_RDDATA = 0x20
SDRAM_PHY_XDR = 1
SDRAM_PHY_DATABITS = 16
SDRAM_PHY_DFI_DATABITS = 16
SDRAM_PHY_PHASES = 1
SDRAM_PHY_CL = 2
SDRAM_PHY_CWL = 2
SDRAM_PHY_RDPHASE = 0
SDRAM_PHY_WRPHASE = 0
SDRAM_PHY_DQ_DQS_RATIO = 8
SDRAM_PHY_MODULES = 2

# csr_register,sdram_dfii_control,0x00001800,1,rw
# csr_register,sdram_dfii_pi0_command,0x00001804,1,rw
# csr_register,sdram_dfii_pi0_command_issue,0x00001808,1,rw
# csr_register,sdram_dfii_pi0_address,0x0000180c,1,rw
# csr_register,sdram_dfii_pi0_baddress,0x00001810,1,rw
# csr_register,sdram_dfii_pi0_wrdata,0x00001814,1,rw
# csr_register,sdram_dfii_pi0_rddata,0x00001818,1,ro

def sdram_dfii_pi0_address_write(a):
    global wb
    wb.regs.sdram_dfii_pi0_address.write(a)

def sdram_dfii_pi0_baddress_write(ba):
    global wb
    wb.regs.sdram_dfii_pi0_baddress.write(ba)

def sdram_dfii_control_write(cmd):
    global wb
    wb.regs.sdram_dfii_control.write(cmd)

def command_p0(cmd):
    global wb
    wb.regs.sdram_dfii_pi0_command.write(cmd)
    wb.regs.sdram_dfii_pi0_command_issue.write(1)

def cdelay(v):
    time.sleep(1)

# software control
wb.regs.sdram_dfii_control.write(0)

# release reset
sdram_dfii_pi0_address_write(0x0)
sdram_dfii_pi0_baddress_write(0)
sdram_dfii_control_write(DFII_CONTROL_ODT|DFII_CONTROL_RESET_N)
cdelay(20000)

# Bring CKE high */
sdram_dfii_pi0_address_write(0x0)
sdram_dfii_pi0_baddress_write(0)
sdram_dfii_control_write(DFII_CONTROL_CKE|DFII_CONTROL_ODT|DFII_CONTROL_RESET_N)
cdelay(20000)

# Precharge All */
sdram_dfii_pi0_address_write(0x400)
sdram_dfii_pi0_baddress_write(0)
command_p0(DFII_COMMAND_RAS|DFII_COMMAND_WE|DFII_COMMAND_CS)

# Load Mode Register / Reset DLL, CL=2, BL=1 */
sdram_dfii_pi0_address_write(0x120)
sdram_dfii_pi0_baddress_write(0)
command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS)
cdelay(200)

# Precharge All */
sdram_dfii_pi0_address_write(0x400)
sdram_dfii_pi0_baddress_write(0)
command_p0(DFII_COMMAND_RAS|DFII_COMMAND_WE|DFII_COMMAND_CS)

# Auto Refresh */
sdram_dfii_pi0_address_write(0x0)
sdram_dfii_pi0_baddress_write(0)
command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_CS)
cdelay(4)

# Auto Refresh */
sdram_dfii_pi0_address_write(0x0)
sdram_dfii_pi0_baddress_write(0)
command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_CS)
cdelay(4)

# Load Mode Register / CL=2, BL=1
sdram_dfii_pi0_address_write(0x20)
sdram_dfii_pi0_baddress_write(0)
command_p0(DFII_COMMAND_RAS| DFII_COMMAND_CAS| DFII_COMMAND_WE| DFII_COMMAND_CS)
cdelay(200)

wb.regs.sdram_dfii_control.write(1)


print("Fill SDRAM with counter:")
mem_write(wb.mems.main_ram.base, [i for i in range(128)])
print("")

print("Dump SDRAM:")
mem_dump(wb.mems.main_ram.base, 128)
print("")

print("Fill SDRAM with 4 32-bit words:")
mem_write(wb.mems.main_ram.base, [0x01234567, 0x89abcdef, 0x5aa55aa5, 0xa55aa55a])
mem_write(wb.mems.main_ram.base+16, [0x01234567, 0x89abcdef, 0x5aa55aa5, 0xa55aa55a])
print("")

print("Dump SDRAM:")
mem_dump(wb.mems.main_ram.base, 128)
print("")

wb.close()