### Use In Amaranth Code

I expect most users to only need to `import` from `sentinel.top`. The top-level
module of the Sentinel CPU is appropriately named `Top`:

```python
from sentinel.top import Top

class MySoC(Elaboratable):
    def __init__(self):
        self.cpu = Top()
        ...

    def elaborate(self, plat):
        m = Module()
        m.submodules.cpu = self.cpu
        ...
```

`Top` exposes a Wishbone Classic bus, and an `irq` input pin as the [interface](https://amaranth-lang.org/rfcs/0002-interfaces.html#interface-definition-library-rfc)
to all other modules in an FPGA design. Of course, `Top`'s also has `clk` and
`rst` lines, which belong to the `sync` [clock domain](https://amaranth-lang.org/docs/amaranth/latest/lang.html#control-domains)
rather than being directly exposed in `Top`'s `Signature`. `sync` is the only
clock domain that Sentinel uses.

See the `AttoSoC` `class` in [examples/attosoc.py](examples/attosoc.py) for a
full working example. A working demo can be generated from this example, as
explained [below](#generate-a-demo-bitstream-for-lattice-icestick).