# %%
from litex.tools.litex_client import RemoteClient

import sdr_init

# %%
wb = RemoteClient(debug=False)
wb.open()

# # #

# software control
wb.regs.sdram_dfii_control.write(0)

# sdram initialization
for i, (comment, a, ba, cmd, delay) in enumerate(sdr_init.init_sequence):
    print(comment)
    wb.regs.sdram_dfii_pi0_address.write(a)
    wb.regs.sdram_dfii_pi0_baddress.write(ba)
    if i < 2:
        wb.regs.sdram_dfii_control.write(cmd)
    else:
        wb.regs.sdram_dfii_pi0_command.write(cmd)
        wb.regs.sdram_dfii_pi0_command_issue.write(1)

# hardware control
wb.regs.sdram_dfii_control.write(sdr_init.dfii_control_sel)

# %%
def seed_to_data(seed, random=True):
    if random:
        return (1664525*seed + 1013904223) & 0xffffffff
    else:
        return seed

def write_pattern(length):
    for i in range(length):
        wb.write(wb.mems.main_ram.base + 4*i, seed_to_data(i))

# %%
def check_pattern(length, debug=False):
    errors = 0
    for i in range(length):
        error = 0
        if wb.read(wb.mems.main_ram.base + 4*i) != seed_to_data(i):
            error = 1
            if debug:
                print("{}: 0x{:08x}, 0x{:08x} KO".format(i, wb.read(wb.mems.main_ram.base + 4*i), seed_to_data(i)))
        else:
            if debug:
                print("{}: 0x{:08x}, 0x{:08x} OK".format(i, wb.read(wb.mems.main_ram.base + 4*i), seed_to_data(i)))
        errors += error
    return errors

# %%
write_pattern(64)
check_pattern(64, debug=True)


# %%