def elaborate(self, plat):
        m = Module()

        # CSR (has to be done first other mem map "frozen" errors?)
        periph_bus = csr.Decoder(addr_width=23, data_width=8, alignment=21,
                                 name="periph")
        periph_bus.add(self.leds.bus)
        if not self.sim:
            periph_bus.add(self.timer.bus)
            periph_bus.add(self.serial.bus)

        # Wishbone
        periph_wb = WishboneCSRBridge(periph_bus.bus, data_width=8)
        self.decoder.add(flipped(self.mem.bus))
        self.decoder.add(flipped(periph_wb.wb_bus), sparse=True)