diff --git a/examples/attosoc.py b/examples/attosoc.py
index 64ea6c7..28b355d 100644
--- a/examples/attosoc.py
+++ b/examples/attosoc.py
@@ -96,7 +96,8 @@ class Leds(Component):
         return self._signature
 
     def __init__(self):
-        self.mux = csr.bus.Multiplexer(addr_width=2, data_width=8, name="gpio")
+        self.mux = csr.bus.Multiplexer(addr_width=21, data_width=8,
+                                       name="gpio")
         self._signature = self.mux.signature
         self._signature.members += {
             "leds": Out(8),
@@ -145,7 +146,7 @@ class Timer(Component):
         return self._signature
 
     def __init__(self):
-        self.mux = csr.bus.Multiplexer(addr_width=1, data_width=8,
+        self.mux = csr.bus.Multiplexer(addr_width=21, data_width=8,
                                        name="timer")
         self._signature = self.mux.signature
         self._signature.members += {
@@ -272,7 +273,7 @@ class WBSerial(Component):
         return self._signature
 
     def __init__(self):
-        self.mux = csr.bus.Multiplexer(addr_width=1, data_width=8,
+        self.mux = csr.bus.Multiplexer(addr_width=21, data_width=8,
                                        name="serial")
         self._signature = self.mux.signature
         self._signature.members += {
@@ -374,7 +375,7 @@ class AttoSoC(Elaboratable):
         m = Module()
 
         # CSR (has to be done first other mem map "frozen" errors?)
-        periph_bus = csr.Decoder(addr_width=25, data_width=8, alignment=23,
+        periph_bus = csr.Decoder(addr_width=23, data_width=8, alignment=21,
                                  name="periph")
         periph_bus.add(self.leds.bus)
         if not self.sim:
@@ -382,9 +383,9 @@ class AttoSoC(Elaboratable):
             periph_bus.add(self.serial.bus)
 
         # Wishbone
-        periph_wb = WishboneCSRBridge(periph_bus.bus, data_width=32)
+        periph_wb = WishboneCSRBridge(periph_bus.bus, data_width=8)
         self.decoder.add(flipped(self.mem.bus))
-        self.decoder.add(flipped(periph_wb.wb_bus))
+        self.decoder.add(flipped(periph_wb.wb_bus), sparse=True)
 
         m.submodules.cpu = self.cpu
         m.submodules.mem = self.mem
diff --git a/sentinel-rt/examples/attosoc.rs b/sentinel-rt/examples/attosoc.rs
index f30dad9..a5d327a 100644
--- a/sentinel-rt/examples/attosoc.rs
+++ b/sentinel-rt/examples/attosoc.rs
@@ -25,23 +25,23 @@ static mut TX_CONS: MaybeUninit<Consumer<'static, u8, 64>> = MaybeUninit::uninit
 // proven that we have exclusive access or have opted into unsafety previously.
 // These are all valid I/O port addresses.
 fn read_timer_int(_cs: CriticalSection) -> u8 {
-    unsafe { read_volatile(0x02800000 as *const u8) }
+    unsafe { read_volatile(0x02200000 as *const u8) }
 }
 
 fn read_serial_int(_cs: CriticalSection) -> u8 {
-    unsafe { read_volatile(0x03000001 as *const u8) }
+    unsafe { read_volatile(0x02400004 as *const u8) }
 }
 
 fn read_serial_rx(_cs: CriticalSection) -> u8 {
-    unsafe { read_volatile(0x03000000 as *const u8) }
+    unsafe { read_volatile(0x02400000 as *const u8) }
 }
 
 fn write_serial_tx(_cs: CriticalSection, val: u8) {
-    unsafe { write_volatile(0x03000000 as *mut u8, val) }
+    unsafe { write_volatile(0x02400000 as *mut u8, val) }
 }
 
 fn read_inp_port(_cs: CriticalSection,) -> u8 {
-    unsafe { read_volatile(0x02000001 as *const u8) }
+    unsafe { read_volatile(0x02000004 as *const u8) }
 }
 
 fn write_leds(_cs: CriticalSection, val: u8) {