diff --git a/core/stellar.py b/core/stellar.py
index 1923805..98f4b14 100644
--- a/core/stellar.py
+++ b/core/stellar.py
@@ -19,6 +19,7 @@ from . import lxbuildenv
 from migen import *
 from migen.genlib.resetsync import AsyncResetSynchronizer
 
+from litex.build.generic_platform import *
 from litex.build.io import DDROutput
 
 from litex.soc.cores.clock.gowin_gw1n import  GW1NPLL
@@ -158,6 +159,23 @@ class BaseSoC(SoCCore):
         self.submodules.lpcbone = LPCBone(platform, lpc_pads)
         self.add_wb_master(self.lpcbone.bus)
 
+        self.platform.add_extension([("sdram_wb", 0,
+            Subsignal("cyc", Pins("fpc:0")),
+            Subsignal("stb", Pins("fpc:1")),
+            Subsignal("ack", Pins("fpc:2"))
+        )])
+
+        wb_sdram = self.bus.slaves["main_ram"]
+        breakout = platform.request("sdram_wb")
+
+        print(dir(breakout))
+
+        self.comb += [
+            breakout.cyc.eq(wb_sdram.cyc),
+            breakout.stb.eq(wb_sdram.stb),
+            breakout.ack.eq(wb_sdram.ack),
+        ]
+
 # Build --------------------------------------------------------------------------------------------
 def main():
     # The LiteX SoC and FPGA build flow is VERY customizable out-of-the-box.