/----------------------------------------------------------------------------\ | | | yosys -- Yosys Open SYnthesis Suite | | | | Copyright (C) 2012 - 2020 Claire Xenia Wolf | | | | Permission to use, copy, modify, and/or distribute this software for any | | purpose with or without fee is hereby granted, provided that the above | | copyright notice and this permission notice appear in all copies. | | | | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | | | \----------------------------------------------------------------------------/ Yosys 0.35+39 (git sha1 031ad38b5, sccache gcc 9.4.0-1ubuntu1~20.04.2 -fPIC -Os) -- Executing script file `top.ys' -- 1. Executing RTLIL frontend. Input filename: top.il 2. Executing SYNTH_ICE40 pass. 2.1. Executing Verilog-2005 frontend: /home/william/.local/bin/../share/yosys/ice40/cells_sim.v Parsing Verilog input from `/home/william/.local/bin/../share/yosys/ice40/cells_sim.v' to AST representation. Generating RTLIL representation for module `\SB_IO'. Generating RTLIL representation for module `\SB_GB_IO'. Generating RTLIL representation for module `\SB_GB'. Generating RTLIL representation for module `\SB_LUT4'. Generating RTLIL representation for module `\SB_CARRY'. Generating RTLIL representation for module `\SB_DFF'. Generating RTLIL representation for module `\SB_DFFE'. Generating RTLIL representation for module `\SB_DFFSR'. Generating RTLIL representation for module `\SB_DFFR'. Generating RTLIL representation for module `\SB_DFFSS'. Generating RTLIL representation for module `\SB_DFFS'. Generating RTLIL representation for module `\SB_DFFESR'. Generating RTLIL representation for module `\SB_DFFER'. Generating RTLIL representation for module `\SB_DFFESS'. Generating RTLIL representation for module `\SB_DFFES'. Generating RTLIL representation for module `\SB_DFFN'. Generating RTLIL representation for module `\SB_DFFNE'. Generating RTLIL representation for module `\SB_DFFNSR'. Generating RTLIL representation for module `\SB_DFFNR'. Generating RTLIL representation for module `\SB_DFFNSS'. Generating RTLIL representation for module `\SB_DFFNS'. Generating RTLIL representation for module `\SB_DFFNESR'. Generating RTLIL representation for module `\SB_DFFNER'. Generating RTLIL representation for module `\SB_DFFNESS'. Generating RTLIL representation for module `\SB_DFFNES'. Generating RTLIL representation for module `\SB_RAM40_4K'. Generating RTLIL representation for module `\SB_RAM40_4KNR'. Generating RTLIL representation for module `\SB_RAM40_4KNW'. Generating RTLIL representation for module `\SB_RAM40_4KNRNW'. Generating RTLIL representation for module `\ICESTORM_LC'. Generating RTLIL representation for module `\SB_PLL40_CORE'. Generating RTLIL representation for module `\SB_PLL40_PAD'. Generating RTLIL representation for module `\SB_PLL40_2_PAD'. Generating RTLIL representation for module `\SB_PLL40_2F_CORE'. Generating RTLIL representation for module `\SB_PLL40_2F_PAD'. Generating RTLIL representation for module `\SB_WARMBOOT'. Generating RTLIL representation for module `\SB_SPRAM256KA'. Generating RTLIL representation for module `\SB_HFOSC'. Generating RTLIL representation for module `\SB_LFOSC'. Generating RTLIL representation for module `\SB_RGBA_DRV'. Generating RTLIL representation for module `\SB_LED_DRV_CUR'. Generating RTLIL representation for module `\SB_RGB_DRV'. Generating RTLIL representation for module `\SB_I2C'. Generating RTLIL representation for module `\SB_SPI'. Generating RTLIL representation for module `\SB_LEDDA_IP'. Generating RTLIL representation for module `\SB_FILTER_50NS'. Generating RTLIL representation for module `\SB_IO_I3C'. Generating RTLIL representation for module `\SB_IO_OD'. Generating RTLIL representation for module `\SB_MAC16'. Generating RTLIL representation for module `\ICESTORM_RAM'. Successfully finished Verilog frontend. 2.2. Executing HIERARCHY pass (managing design hierarchy). 2.2.1. Analyzing design hierarchy.. Top module: \top Used module: \top.pin_clk12_0 Used module: \top.pin_inp_0 Used module: \top.pin_uart_0__dcd Used module: \top.pin_uart_0__dsr Used module: \top.pin_uart_0__dtr Used module: \top.pin_uart_0__cts Used module: \top.pin_uart_0__rts Used module: \top.pin_uart_0__tx Used module: \top.pin_uart_0__rx Used module: \top.pin_led_4 Used module: \top.pin_led_3 Used module: \top.pin_led_2 Used module: \top.pin_led_1 Used module: \top.pin_led_0 Used module: \top.cd_sync Used module: \top.serial Used module: \top.serial.ser_internal Used module: \top.timer Used module: \top.decoder Used module: \top.leds Used module: \top.mem Used module: \top.cpu Used module: \top.cpu.exception_router Used module: \top.cpu.decode Used module: \top.cpu.datapath Used module: \top.cpu.datapath.csrfile Used module: \top.cpu.datapath.regfile Used module: \top.cpu.datapath.pc_mod Used module: \top.cpu.control Used module: \top.cpu.control.sequencer Used module: \top.cpu.control.ucoderom Used module: \top.cpu.alu Used module: \top.cpu.alu.sal Used module: \top.cpu.alu.srl Used module: \top.cpu.alu.sll Used module: \top.cpu.alu.xor Used module: \top.cpu.alu.or_ Used module: \top.cpu.alu.and_ Used module: \top.cpu.alu.sub Used module: \top.cpu.alu.add 2.2.2. Analyzing design hierarchy.. Top module: \top Used module: \top.pin_clk12_0 Used module: \top.pin_inp_0 Used module: \top.pin_uart_0__dcd Used module: \top.pin_uart_0__dsr Used module: \top.pin_uart_0__dtr Used module: \top.pin_uart_0__cts Used module: \top.pin_uart_0__rts Used module: \top.pin_uart_0__tx Used module: \top.pin_uart_0__rx Used module: \top.pin_led_4 Used module: \top.pin_led_3 Used module: \top.pin_led_2 Used module: \top.pin_led_1 Used module: \top.pin_led_0 Used module: \top.cd_sync Used module: \top.serial Used module: \top.serial.ser_internal Used module: \top.timer Used module: \top.decoder Used module: \top.leds Used module: \top.mem Used module: \top.cpu Used module: \top.cpu.exception_router Used module: \top.cpu.decode Used module: \top.cpu.datapath Used module: \top.cpu.datapath.csrfile Used module: \top.cpu.datapath.regfile Used module: \top.cpu.datapath.pc_mod Used module: \top.cpu.control Used module: \top.cpu.control.sequencer Used module: \top.cpu.control.ucoderom Used module: \top.cpu.alu Used module: \top.cpu.alu.sal Used module: \top.cpu.alu.srl Used module: \top.cpu.alu.sll Used module: \top.cpu.alu.xor Used module: \top.cpu.alu.or_ Used module: \top.cpu.alu.and_ Used module: \top.cpu.alu.sub Used module: \top.cpu.alu.add Removed 0 unused modules. 2.3. Executing PROC pass (convert processes to netlists). 2.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `top.$group_15'. Removing empty process `top.$group_7'. Removing empty process `top.decoder.$group_15'. Removing empty process `top.decoder.$group_10'. Cleaned up 0 empty switches. 2.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:1414$241 in module SB_DFFNES. Marked 1 switch rules as full_case in process $proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:1353$234 in module SB_DFFNESS. Marked 1 switch rules as full_case in process $proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:1273$230 in module SB_DFFNER. Marked 1 switch rules as full_case in process $proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:1212$223 in module SB_DFFNESR. Marked 1 switch rules as full_case in process $proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:1138$220 in module SB_DFFNS. Marked 1 switch rules as full_case in process $proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:1088$217 in module SB_DFFNSS. Marked 1 switch rules as full_case in process $proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:1017$214 in module SB_DFFNR. Marked 1 switch rules as full_case in process $proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:967$211 in module SB_DFFNSR. Marked 1 switch rules as full_case in process $proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:803$203 in module SB_DFFES. Marked 1 switch rules as full_case in process $proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:742$196 in module SB_DFFESS. Marked 1 switch rules as full_case in process $proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:662$192 in module SB_DFFER. Marked 1 switch rules as full_case in process $proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:601$185 in module SB_DFFESR. Marked 1 switch rules as full_case in process $proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:527$182 in module SB_DFFS. Marked 1 switch rules as full_case in process $proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:477$179 in module SB_DFFSS. Marked 1 switch rules as full_case in process $proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:406$176 in module SB_DFFR. Marked 1 switch rules as full_case in process $proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:356$173 in module SB_DFFSR. Marked 1 switch rules as full_case in process $group_2 in module top.cd_sync. Marked 1 switch rules as full_case in process $group_11 in module top.serial. Marked 2 switch rules as full_case in process $group_11 in module top.serial.ser_internal. Marked 2 switch rules as full_case in process $group_10 in module top.serial.ser_internal. Marked 2 switch rules as full_case in process $group_9 in module top.serial.ser_internal. Marked 1 switch rules as full_case in process $group_8 in module top.serial.ser_internal. Marked 2 switch rules as full_case in process $group_7 in module top.serial.ser_internal. Marked 2 switch rules as full_case in process $group_4 in module top.serial.ser_internal. Marked 2 switch rules as full_case in process $group_3 in module top.serial.ser_internal. Marked 2 switch rules as full_case in process $group_2 in module top.serial.ser_internal. Marked 1 switch rules as full_case in process $group_3 in module top.timer. Marked 1 switch rules as full_case in process $group_2 in module top.leds. Marked 1 switch rules as full_case in process $group_6 in module top.mem. Marked 1 switch rules as full_case in process $group_41 in module top.cpu. Marked 1 switch rules as full_case in process $group_40 in module top.cpu. Marked 1 switch rules as full_case in process $group_39 in module top.cpu. Marked 2 switch rules as full_case in process $group_38 in module top.cpu. Marked 3 switch rules as full_case in process $group_35 in module top.cpu. Marked 1 switch rules as full_case in process $group_34 in module top.cpu. Marked 2 switch rules as full_case in process $group_25 in module top.cpu. Marked 2 switch rules as full_case in process $group_11 in module top.cpu. Marked 3 switch rules as full_case in process $group_10 in module top.cpu. Marked 1 switch rules as full_case in process $group_19 in module top.cpu.decode. Marked 4 switch rules as full_case in process $group_18 in module top.cpu.decode. Marked 5 switch rules as full_case in process $group_10 in module top.cpu.decode. Marked 1 switch rules as full_case in process $group_8 in module top.cpu.decode. Marked 1 switch rules as full_case in process $group_7 in module top.cpu.decode. Marked 1 switch rules as full_case in process $group_33 in module top.cpu.control. Marked 1 switch rules as full_case in process $group_32 in module top.cpu.control. Marked 4 switch rules as full_case in process $group_2 in module top.cpu.control.sequencer. Removed a total of 0 dead cases. 2.3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 259 redundant assignments. Promoted 251 assignments to connections. 2.3.4. Executing PROC_INIT pass (extract init attributes). Found init rule in `\SB_DFFNES.$proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:0$244'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFNESS.$proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:0$240'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFNER.$proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:0$233'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFNESR.$proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:0$229'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFNS.$proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:0$222'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFNSS.$proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:0$219'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFNR.$proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:0$216'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFNSR.$proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:0$213'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFNE.$proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:0$210'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFN.$proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:0$208'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFES.$proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:0$206'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFESS.$proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:0$202'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFER.$proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:0$195'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFESR.$proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:0$191'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFS.$proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:0$184'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFSS.$proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:0$181'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFR.$proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:0$178'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFSR.$proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:0$175'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFE.$proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:0$172'. Set init value: \Q = 1'0 Found init rule in `\SB_DFF.$proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:0$170'. Set init value: \Q = 1'0 2.3.5. Executing PROC_ARST pass (detect async resets in processes). Found async reset \S in `\SB_DFFNES.$proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:1414$241'. Found async reset \R in `\SB_DFFNER.$proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:1273$230'. Found async reset \S in `\SB_DFFNS.$proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:1138$220'. Found async reset \R in `\SB_DFFNR.$proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:1017$214'. Found async reset \S in `\SB_DFFES.$proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:803$203'. Found async reset \R in `\SB_DFFER.$proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:662$192'. Found async reset \S in `\SB_DFFS.$proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:527$182'. Found async reset \R in `\SB_DFFR.$proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:406$176'. 2.3.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 1 switch. 2.3.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\SB_DFFNES.$proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:0$244'. Creating decoders for process `\SB_DFFNES.$proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:1414$241'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFNESS.$proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:0$240'. Creating decoders for process `\SB_DFFNESS.$proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:1353$234'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFNER.$proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:0$233'. Creating decoders for process `\SB_DFFNER.$proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:1273$230'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFNESR.$proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:0$229'. Creating decoders for process `\SB_DFFNESR.$proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:1212$223'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFNS.$proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:0$222'. Creating decoders for process `\SB_DFFNS.$proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:1138$220'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFNSS.$proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:0$219'. Creating decoders for process `\SB_DFFNSS.$proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:1088$217'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFNR.$proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:0$216'. Creating decoders for process `\SB_DFFNR.$proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:1017$214'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFNSR.$proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:0$213'. Creating decoders for process `\SB_DFFNSR.$proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:967$211'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFNE.$proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:0$210'. Creating decoders for process `\SB_DFFNE.$proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:922$209'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFN.$proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:0$208'. Creating decoders for process `\SB_DFFN.$proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:882$207'. Creating decoders for process `\SB_DFFES.$proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:0$206'. Creating decoders for process `\SB_DFFES.$proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:803$203'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFESS.$proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:0$202'. Creating decoders for process `\SB_DFFESS.$proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:742$196'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFER.$proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:0$195'. Creating decoders for process `\SB_DFFER.$proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:662$192'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFESR.$proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:0$191'. Creating decoders for process `\SB_DFFESR.$proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:601$185'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFS.$proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:0$184'. Creating decoders for process `\SB_DFFS.$proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:527$182'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFSS.$proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:0$181'. Creating decoders for process `\SB_DFFSS.$proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:477$179'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFR.$proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:0$178'. Creating decoders for process `\SB_DFFR.$proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:406$176'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFSR.$proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:0$175'. Creating decoders for process `\SB_DFFSR.$proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:356$173'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFE.$proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:0$172'. Creating decoders for process `\SB_DFFE.$proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:311$171'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFF.$proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:0$170'. Creating decoders for process `\SB_DFF.$proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:271$169'. Creating decoders for process `\top.$group_46'. Creating decoders for process `\top.$group_45'. Creating decoders for process `\top.$group_44'. Creating decoders for process `\top.$group_43'. Creating decoders for process `\top.$group_42'. Creating decoders for process `\top.$group_41'. Creating decoders for process `\top.$group_40'. Creating decoders for process `\top.$group_39'. Creating decoders for process `\top.$group_38'. Creating decoders for process `\top.$group_37'. Creating decoders for process `\top.$group_36'. Creating decoders for process `\top.$group_35'. Creating decoders for process `\top.$group_34'. Creating decoders for process `\top.$group_33'. Creating decoders for process `\top.$group_32'. Creating decoders for process `\top.$group_31'. Creating decoders for process `\top.$group_30'. Creating decoders for process `\top.$group_29'. Creating decoders for process `\top.$group_28'. Creating decoders for process `\top.$group_27'. Creating decoders for process `\top.$group_26'. Creating decoders for process `\top.$group_25'. Creating decoders for process `\top.$group_24'. Creating decoders for process `\top.$group_23'. Creating decoders for process `\top.$group_22'. Creating decoders for process `\top.$group_21'. Creating decoders for process `\top.$group_20'. Creating decoders for process `\top.$group_19'. Creating decoders for process `\top.$group_18'. Creating decoders for process `\top.$group_17'. Creating decoders for process `\top.$group_16'. Creating decoders for process `\top.$group_48'. Creating decoders for process `\top.$group_14'. Creating decoders for process `\top.$group_13'. Creating decoders for process `\top.$group_12'. Creating decoders for process `\top.$group_11'. Creating decoders for process `\top.$group_10'. Creating decoders for process `\top.$group_9'. Creating decoders for process `\top.$group_8'. Creating decoders for process `\top.$group_47'. Creating decoders for process `\top.$group_6'. Creating decoders for process `\top.$group_5'. Creating decoders for process `\top.$group_4'. Creating decoders for process `\top.$group_3'. Creating decoders for process `\top.$group_2'. Creating decoders for process `\top.$group_1'. Creating decoders for process `\top.$group_0'. Creating decoders for process `\top.cd_sync.$group_4'. Creating decoders for process `\top.cd_sync.$group_3'. Creating decoders for process `\top.cd_sync.$group_2'. 1/1: \timer$next Creating decoders for process `\top.cd_sync.$group_1'. 1/1: \ready$next Creating decoders for process `\top.cd_sync.$group_0'. Creating decoders for process `\top.serial.$group_11'. 1/1: \bus__ack$next Creating decoders for process `\top.serial.$group_10'. 1/1: \tx_ack_irq$next Creating decoders for process `\top.serial.$group_9'. 1/1: \rx_rdy_irq$next Creating decoders for process `\top.serial.$group_8'. 1/1: \ser_internal_tx_rdy Creating decoders for process `\top.serial.$group_7'. 1/1: \ser_internal_tx_data Creating decoders for process `\top.serial.$group_6'. 1/1: \ser_internal_rx_ack Creating decoders for process `\top.serial.$group_5'. 1/3: \bus__dat_r$next [31:10] 2/3: \bus__dat_r$next [7:0] 3/3: \bus__dat_r$next [9:8] Creating decoders for process `\top.serial.$group_4'. 1/1: \tx_ack_prev$next Creating decoders for process `\top.serial.$group_3'. 1/1: \rx_rdy_prev$next Creating decoders for process `\top.serial.$group_2'. Creating decoders for process `\top.serial.$group_1'. Creating decoders for process `\top.serial.$group_0'. Creating decoders for process `\top.serial.ser_internal.$group_11'. 1/1: \rx_shreg$next Creating decoders for process `\top.serial.ser_internal.$group_10'. 1/1: \rx_phase$next Creating decoders for process `\top.serial.ser_internal.$group_9'. 1/1: \rx_count$next Creating decoders for process `\top.serial.ser_internal.$group_8'. 1/1: \rx_ovf$next Creating decoders for process `\top.serial.ser_internal.$group_7'. 1/1: \rx_rdy$next Creating decoders for process `\top.serial.ser_internal.$group_6'. 1/1: \rx_err Creating decoders for process `\top.serial.ser_internal.$group_5'. Creating decoders for process `\top.serial.ser_internal.$group_4'. 1/1: \tx_phase$next Creating decoders for process `\top.serial.ser_internal.$group_3'. 1/1: \tx_count$next Creating decoders for process `\top.serial.ser_internal.$group_2'. 1/1: \tx_shreg$next Creating decoders for process `\top.serial.ser_internal.$group_1'. 1/1: \tx_ack Creating decoders for process `\top.serial.ser_internal.$group_0'. Creating decoders for process `\top.timer.$group_3'. 1/1: \bus__ack$next Creating decoders for process `\top.timer.$group_2'. 1/1: \bus__dat_r$next Creating decoders for process `\top.timer.$group_1'. Creating decoders for process `\top.timer.$group_0'. 1/2: \prescalar$next [14] 2/2: \prescalar$next [13:0] Creating decoders for process `\top.decoder.$group_23'. 1/1: \timer__cyc Creating decoders for process `\top.decoder.$group_22'. 1/1: \led__cyc Creating decoders for process `\top.decoder.$group_21'. 1/1: \bus__dat_r Creating decoders for process `\top.decoder.$group_20'. 1/1: \mem__cyc Creating decoders for process `\top.decoder.$group_19'. Creating decoders for process `\top.decoder.$group_18'. Creating decoders for process `\top.decoder.$group_17'. Creating decoders for process `\top.decoder.$group_16'. Creating decoders for process `\top.decoder.$group_25'. Creating decoders for process `\top.decoder.$group_14'. Creating decoders for process `\top.decoder.$group_13'. Creating decoders for process `\top.decoder.$group_12'. Creating decoders for process `\top.decoder.$group_11'. Creating decoders for process `\top.decoder.$group_24'. 1/1: \serial__cyc Creating decoders for process `\top.decoder.$group_9'. Creating decoders for process `\top.decoder.$group_8'. Creating decoders for process `\top.decoder.$group_7'. Creating decoders for process `\top.decoder.$group_6'. Creating decoders for process `\top.decoder.$group_5'. Creating decoders for process `\top.decoder.$group_4'. Creating decoders for process `\top.decoder.$group_3'. Creating decoders for process `\top.decoder.$group_2'. Creating decoders for process `\top.decoder.$group_1'. Creating decoders for process `\top.decoder.$group_0'. Creating decoders for process `\top.leds.$group_2'. 1/1: \bus__ack$next Creating decoders for process `\top.leds.$group_1'. 1/1: \bus__dat_r$next Creating decoders for process `\top.leds.$group_0'. 1/1: \leds$next Creating decoders for process `\top.mem.$group_6'. 1/1: \bus__ack$next Creating decoders for process `\top.mem.$group_5'. 1/1: \mem_w_en Creating decoders for process `\top.mem.$group_4'. Creating decoders for process `\top.mem.$group_3'. Creating decoders for process `\top.mem.$group_2'. Creating decoders for process `\top.mem.$group_1'. Creating decoders for process `\top.mem.$group_0'. Creating decoders for process `\top.cpu.$group_49'. Creating decoders for process `\top.cpu.$group_48'. Creating decoders for process `\top.cpu.$group_47'. Creating decoders for process `\top.cpu.$group_46'. Creating decoders for process `\top.cpu.$group_45'. Creating decoders for process `\top.cpu.$group_44'. Creating decoders for process `\top.cpu.$group_43'. Creating decoders for process `\top.cpu.$group_42'. Creating decoders for process `\top.cpu.$group_41'. 1/1: \datapath_csr__adr Creating decoders for process `\top.cpu.$group_40'. 1/1: \datapath_gp__ctrl__allow_zero_wr Creating decoders for process `\top.cpu.$group_39'. 1/1: \reg_w_adr Creating decoders for process `\top.cpu.$group_38'. 1/1: \reg_r_adr Creating decoders for process `\top.cpu.$group_37'. Creating decoders for process `\top.cpu.$group_36'. Creating decoders for process `\top.cpu.$group_35'. 1/1: \bus__sel Creating decoders for process `\top.cpu.$group_34'. 1/1: \bus__adr Creating decoders for process `\top.cpu.$group_33'. 1/1: \data_adr$next Creating decoders for process `\top.cpu.$group_32'. Creating decoders for process `\top.cpu.$group_31'. Creating decoders for process `\top.cpu.$group_30'. Creating decoders for process `\top.cpu.$group_29'. Creating decoders for process `\top.cpu.$group_28'. Creating decoders for process `\top.cpu.$group_27'. Creating decoders for process `\top.cpu.$group_26'. Creating decoders for process `\top.cpu.$group_25'. 1/4: \write_data$next [31:24] 2/4: \write_data$next [23:16] 3/4: \write_data$next [15:8] 4/4: \write_data$next [7:0] Creating decoders for process `\top.cpu.$group_24'. Creating decoders for process `\top.cpu.$group_23'. Creating decoders for process `\top.cpu.$group_22'. Creating decoders for process `\top.cpu.$group_21'. Creating decoders for process `\top.cpu.$group_20'. Creating decoders for process `\top.cpu.$group_19'. Creating decoders for process `\top.cpu.$group_18'. Creating decoders for process `\top.cpu.$group_17'. Creating decoders for process `\top.cpu.$group_16'. Creating decoders for process `\top.cpu.$group_15'. Creating decoders for process `\top.cpu.$group_14'. Creating decoders for process `\top.cpu.$group_13'. Creating decoders for process `\top.cpu.$group_12'. Creating decoders for process `\top.cpu.$group_11'. 1/1: \raw_dat_r Creating decoders for process `\top.cpu.$group_10'. 1/1: \b_input$next Creating decoders for process `\top.cpu.$group_9'. 1/1: \a_input$next Creating decoders for process `\top.cpu.$group_8'. Creating decoders for process `\top.cpu.$group_7'. Creating decoders for process `\top.cpu.$group_6'. Creating decoders for process `\top.cpu.$group_5'. Creating decoders for process `\top.cpu.$group_4'. Creating decoders for process `\top.cpu.$group_3'. Creating decoders for process `\top.cpu.$group_2'. Creating decoders for process `\top.cpu.$group_1'. Creating decoders for process `\top.cpu.$group_0'. Creating decoders for process `\top.cpu.exception_router.$group_3'. 1/2: \mcause_latch$next [31] 2/2: \mcause_latch$next [30:0] Creating decoders for process `\top.cpu.exception_router.$group_2'. 1/1: \exception Creating decoders for process `\top.cpu.exception_router.$group_1'. Creating decoders for process `\top.cpu.exception_router.$group_0'. Creating decoders for process `\top.cpu.decode.$group_21'. 1/1: \ro0 Creating decoders for process `\top.cpu.decode.$group_20'. 1/1: \illegal Creating decoders for process `\top.cpu.decode.$group_19'. 1/1: \csr_encoding$next Creating decoders for process `\top.cpu.decode.$group_18'. 1/1: \requested_op$next Creating decoders for process `\top.cpu.decode.$group_17'. 1/1: \imm$next Creating decoders for process `\top.cpu.decode.$group_16'. 1/1: \dst$next Creating decoders for process `\top.cpu.decode.$group_15'. 1/1: \src_b$next Creating decoders for process `\top.cpu.decode.$group_14'. 1/1: \src_a$next Creating decoders for process `\top.cpu.decode.$group_13'. 1/1: \csr_ro_space$next Creating decoders for process `\top.cpu.decode.$group_12'. 1/1: \csr_op$next Creating decoders for process `\top.cpu.decode.$group_11'. 1/1: \csr_quadrant$next Creating decoders for process `\top.cpu.decode.$group_10'. 1/1: \exception$next Creating decoders for process `\top.cpu.decode.$group_9'. 1/1: \e_type$next Creating decoders for process `\top.cpu.decode.$group_8'. 1/1: \forward_csr$next Creating decoders for process `\top.cpu.decode.$group_7'. 1/1: \csr_map$next Creating decoders for process `\top.cpu.decode.$group_6'. Creating decoders for process `\top.cpu.decode.$group_5'. Creating decoders for process `\top.cpu.decode.$group_4'. Creating decoders for process `\top.cpu.decode.$group_3'. Creating decoders for process `\top.cpu.decode.$group_2'. Creating decoders for process `\top.cpu.decode.$group_1'. Creating decoders for process `\top.cpu.decode.$group_0'. Creating decoders for process `\top.cpu.datapath.$group_26'. Creating decoders for process `\top.cpu.datapath.$group_25'. Creating decoders for process `\top.cpu.datapath.$group_24'. Creating decoders for process `\top.cpu.datapath.$group_23'. Creating decoders for process `\top.cpu.datapath.$group_22'. Creating decoders for process `\top.cpu.datapath.$group_21'. Creating decoders for process `\top.cpu.datapath.$group_20'. Creating decoders for process `\top.cpu.datapath.$group_19'. Creating decoders for process `\top.cpu.datapath.$group_18'. Creating decoders for process `\top.cpu.datapath.$group_17'. Creating decoders for process `\top.cpu.datapath.$group_16'. Creating decoders for process `\top.cpu.datapath.$group_15'. Creating decoders for process `\top.cpu.datapath.$group_14'. Creating decoders for process `\top.cpu.datapath.$group_13'. Creating decoders for process `\top.cpu.datapath.$group_12'. Creating decoders for process `\top.cpu.datapath.$group_11'. Creating decoders for process `\top.cpu.datapath.$group_10'. Creating decoders for process `\top.cpu.datapath.$group_9'. Creating decoders for process `\top.cpu.datapath.$group_8'. Creating decoders for process `\top.cpu.datapath.$group_7'. Creating decoders for process `\top.cpu.datapath.$group_6'. Creating decoders for process `\top.cpu.datapath.$group_5'. Creating decoders for process `\top.cpu.datapath.$group_4'. Creating decoders for process `\top.cpu.datapath.$group_3'. Creating decoders for process `\top.cpu.datapath.$group_2'. Creating decoders for process `\top.cpu.datapath.$group_1'. Creating decoders for process `\top.cpu.datapath.$group_0'. Creating decoders for process `\top.cpu.datapath.csrfile.$group_11'. Creating decoders for process `\top.cpu.datapath.csrfile.$group_10'. 1/1: \prev_csr_adr$next Creating decoders for process `\top.cpu.datapath.csrfile.$group_9'. 1/8: \read_buf$next [31:13] 2/8: \read_buf$next [10:8] 3/8: \read_buf$next [6:4] 4/8: \read_buf$next [3] 5/8: \read_buf$next [2:0] 6/8: \read_buf$next [12] 7/8: \read_buf$next [11] 8/8: \read_buf$next [7] Creating decoders for process `\top.cpu.datapath.csrfile.$group_8'. 1/3: \mie$next [31:12] 2/3: \mie$next [10:0] 3/3: \mie$next [11] Creating decoders for process `\top.cpu.datapath.csrfile.$group_7'. 1/5: \mstatus$next [31:8] 2/5: \mstatus$next [6:4] 3/5: \mstatus$next [3] 4/5: \mstatus$next [2:0] 5/5: \mstatus$next [7] Creating decoders for process `\top.cpu.datapath.csrfile.$group_6'. Creating decoders for process `\top.cpu.datapath.csrfile.$group_5'. 1/1: \priv__dat_w [1:0] Creating decoders for process `\top.cpu.datapath.csrfile.$group_4'. Creating decoders for process `\top.cpu.datapath.csrfile.$group_3'. 1/1: \pub__dat_r Creating decoders for process `\top.cpu.datapath.csrfile.$group_2'. Creating decoders for process `\top.cpu.datapath.csrfile.$group_1'. Creating decoders for process `\top.cpu.datapath.csrfile.$group_0'. Creating decoders for process `\top.cpu.datapath.regfile.$group_6'. 1/1: \mem_w_en Creating decoders for process `\top.cpu.datapath.regfile.$group_5'. 1/1: \mem_r_en Creating decoders for process `\top.cpu.datapath.regfile.$group_4'. 1/1: \mem_w_data Creating decoders for process `\top.cpu.datapath.regfile.$group_3'. 1/1: \mem_w_addr Creating decoders for process `\top.cpu.datapath.regfile.$group_2'. 1/1: \mem_r_addr Creating decoders for process `\top.cpu.datapath.regfile.$group_1'. Creating decoders for process `\top.cpu.datapath.regfile.$group_0'. Creating decoders for process `\top.cpu.datapath.pc_mod.$group_0'. 1/1: \dat_r$next Creating decoders for process `\top.cpu.control.$group_33'. 1/1: \test Creating decoders for process `\top.cpu.control.$group_32'. 1/1: \raw_test Creating decoders for process `\top.cpu.control.$group_31'. Creating decoders for process `\top.cpu.control.$group_30'. Creating decoders for process `\top.cpu.control.$group_29'. Creating decoders for process `\top.cpu.control.$group_28'. Creating decoders for process `\top.cpu.control.$group_27'. Creating decoders for process `\top.cpu.control.$group_26'. Creating decoders for process `\top.cpu.control.$group_25'. Creating decoders for process `\top.cpu.control.$group_24'. Creating decoders for process `\top.cpu.control.$group_23'. Creating decoders for process `\top.cpu.control.$group_22'. Creating decoders for process `\top.cpu.control.$group_21'. Creating decoders for process `\top.cpu.control.$group_20'. Creating decoders for process `\top.cpu.control.$group_19'. Creating decoders for process `\top.cpu.control.$group_18'. Creating decoders for process `\top.cpu.control.$group_17'. Creating decoders for process `\top.cpu.control.$group_16'. Creating decoders for process `\top.cpu.control.$group_15'. Creating decoders for process `\top.cpu.control.$group_14'. Creating decoders for process `\top.cpu.control.$group_13'. Creating decoders for process `\top.cpu.control.$group_12'. Creating decoders for process `\top.cpu.control.$group_11'. Creating decoders for process `\top.cpu.control.$group_10'. Creating decoders for process `\top.cpu.control.$group_9'. Creating decoders for process `\top.cpu.control.$group_8'. Creating decoders for process `\top.cpu.control.$group_7'. Creating decoders for process `\top.cpu.control.$group_6'. Creating decoders for process `\top.cpu.control.$group_5'. Creating decoders for process `\top.cpu.control.$group_4'. Creating decoders for process `\top.cpu.control.$group_3'. Creating decoders for process `\top.cpu.control.$group_2'. Creating decoders for process `\top.cpu.control.$group_1'. Creating decoders for process `\top.cpu.control.$group_0'. Creating decoders for process `\top.cpu.control.sequencer.$group_2'. 1/1: \adr Creating decoders for process `\top.cpu.control.sequencer.$group_1'. 1/1: \ice40_rst_guard$next Creating decoders for process `\top.cpu.control.sequencer.$group_0'. 1/1: \next_adr$next Creating decoders for process `\top.cpu.control.ucoderom.$group_1'. Creating decoders for process `\top.cpu.control.ucoderom.$group_0'. Creating decoders for process `\top.cpu.alu.$group_20'. Creating decoders for process `\top.cpu.alu.$group_19'. 1/2: \data__o$next [31:1] 2/2: \data__o$next [0] Creating decoders for process `\top.cpu.alu.$group_18'. 1/1: \o_mux Creating decoders for process `\top.cpu.alu.$group_17'. Creating decoders for process `\top.cpu.alu.$group_16'. Creating decoders for process `\top.cpu.alu.$group_15'. Creating decoders for process `\top.cpu.alu.$group_14'. Creating decoders for process `\top.cpu.alu.$group_13'. Creating decoders for process `\top.cpu.alu.$group_12'. Creating decoders for process `\top.cpu.alu.$group_11'. Creating decoders for process `\top.cpu.alu.$group_10'. Creating decoders for process `\top.cpu.alu.$group_9'. Creating decoders for process `\top.cpu.alu.$group_8'. Creating decoders for process `\top.cpu.alu.$group_7'. Creating decoders for process `\top.cpu.alu.$group_6'. Creating decoders for process `\top.cpu.alu.$group_5'. Creating decoders for process `\top.cpu.alu.$group_4'. Creating decoders for process `\top.cpu.alu.$group_3'. Creating decoders for process `\top.cpu.alu.$group_2'. Creating decoders for process `\top.cpu.alu.$group_1'. 1/1: \mod_b [31] Creating decoders for process `\top.cpu.alu.$group_0'. 1/1: \mod_a [31] Creating decoders for process `\top.cpu.alu.sal.$group_0'. Creating decoders for process `\top.cpu.alu.srl.$group_0'. Creating decoders for process `\top.cpu.alu.sll.$group_0'. Creating decoders for process `\top.cpu.alu.xor.$group_0'. Creating decoders for process `\top.cpu.alu.or_.$group_0'. Creating decoders for process `\top.cpu.alu.and_.$group_0'. Creating decoders for process `\top.cpu.alu.sub.$group_0'. Creating decoders for process `\top.cpu.alu.add.$group_0'. 2.3.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2.3.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `\SB_DFFNES.\Q' using process `\SB_DFFNES.$proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:1414$241'. created $adff cell `$procdff$1233' with negative edge clock and positive level reset. Creating register for signal `\SB_DFFNESS.\Q' using process `\SB_DFFNESS.$proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:1353$234'. created $dff cell `$procdff$1234' with negative edge clock. Creating register for signal `\SB_DFFNER.\Q' using process `\SB_DFFNER.$proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:1273$230'. created $adff cell `$procdff$1235' with negative edge clock and positive level reset. Creating register for signal `\SB_DFFNESR.\Q' using process `\SB_DFFNESR.$proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:1212$223'. created $dff cell `$procdff$1236' with negative edge clock. Creating register for signal `\SB_DFFNS.\Q' using process `\SB_DFFNS.$proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:1138$220'. created $adff cell `$procdff$1237' with negative edge clock and positive level reset. Creating register for signal `\SB_DFFNSS.\Q' using process `\SB_DFFNSS.$proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:1088$217'. created $dff cell `$procdff$1238' with negative edge clock. Creating register for signal `\SB_DFFNR.\Q' using process `\SB_DFFNR.$proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:1017$214'. created $adff cell `$procdff$1239' with negative edge clock and positive level reset. Creating register for signal `\SB_DFFNSR.\Q' using process `\SB_DFFNSR.$proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:967$211'. created $dff cell `$procdff$1240' with negative edge clock. Creating register for signal `\SB_DFFNE.\Q' using process `\SB_DFFNE.$proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:922$209'. created $dff cell `$procdff$1241' with negative edge clock. Creating register for signal `\SB_DFFN.\Q' using process `\SB_DFFN.$proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:882$207'. created $dff cell `$procdff$1242' with negative edge clock. Creating register for signal `\SB_DFFES.\Q' using process `\SB_DFFES.$proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:803$203'. created $adff cell `$procdff$1243' with positive edge clock and positive level reset. Creating register for signal `\SB_DFFESS.\Q' using process `\SB_DFFESS.$proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:742$196'. created $dff cell `$procdff$1244' with positive edge clock. Creating register for signal `\SB_DFFER.\Q' using process `\SB_DFFER.$proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:662$192'. created $adff cell `$procdff$1245' with positive edge clock and positive level reset. Creating register for signal `\SB_DFFESR.\Q' using process `\SB_DFFESR.$proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:601$185'. created $dff cell `$procdff$1246' with positive edge clock. Creating register for signal `\SB_DFFS.\Q' using process `\SB_DFFS.$proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:527$182'. created $adff cell `$procdff$1247' with positive edge clock and positive level reset. Creating register for signal `\SB_DFFSS.\Q' using process `\SB_DFFSS.$proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:477$179'. created $dff cell `$procdff$1248' with positive edge clock. Creating register for signal `\SB_DFFR.\Q' using process `\SB_DFFR.$proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:406$176'. created $adff cell `$procdff$1249' with positive edge clock and positive level reset. Creating register for signal `\SB_DFFSR.\Q' using process `\SB_DFFSR.$proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:356$173'. created $dff cell `$procdff$1250' with positive edge clock. Creating register for signal `\SB_DFFE.\Q' using process `\SB_DFFE.$proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:311$171'. created $dff cell `$procdff$1251' with positive edge clock. Creating register for signal `\SB_DFF.\Q' using process `\SB_DFF.$proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:271$169'. created $dff cell `$procdff$1252' with positive edge clock. 2.3.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2.3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `SB_DFFNES.$proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:0$244'. Found and cleaned up 1 empty switch in `\SB_DFFNES.$proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:1414$241'. Removing empty process `SB_DFFNES.$proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:1414$241'. Removing empty process `SB_DFFNESS.$proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:0$240'. Found and cleaned up 2 empty switches in `\SB_DFFNESS.$proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:1353$234'. Removing empty process `SB_DFFNESS.$proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:1353$234'. Removing empty process `SB_DFFNER.$proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:0$233'. Found and cleaned up 1 empty switch in `\SB_DFFNER.$proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:1273$230'. Removing empty process `SB_DFFNER.$proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:1273$230'. Removing empty process `SB_DFFNESR.$proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:0$229'. Found and cleaned up 2 empty switches in `\SB_DFFNESR.$proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:1212$223'. Removing empty process `SB_DFFNESR.$proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:1212$223'. Removing empty process `SB_DFFNS.$proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:0$222'. Removing empty process `SB_DFFNS.$proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:1138$220'. Removing empty process `SB_DFFNSS.$proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:0$219'. Found and cleaned up 1 empty switch in `\SB_DFFNSS.$proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:1088$217'. Removing empty process `SB_DFFNSS.$proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:1088$217'. Removing empty process `SB_DFFNR.$proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:0$216'. Removing empty process `SB_DFFNR.$proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:1017$214'. Removing empty process `SB_DFFNSR.$proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:0$213'. Found and cleaned up 1 empty switch in `\SB_DFFNSR.$proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:967$211'. Removing empty process `SB_DFFNSR.$proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:967$211'. Removing empty process `SB_DFFNE.$proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:0$210'. Found and cleaned up 1 empty switch in `\SB_DFFNE.$proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:922$209'. Removing empty process `SB_DFFNE.$proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:922$209'. Removing empty process `SB_DFFN.$proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:0$208'. Removing empty process `SB_DFFN.$proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:882$207'. Removing empty process `SB_DFFES.$proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:0$206'. Found and cleaned up 1 empty switch in `\SB_DFFES.$proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:803$203'. Removing empty process `SB_DFFES.$proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:803$203'. Removing empty process `SB_DFFESS.$proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:0$202'. Found and cleaned up 2 empty switches in `\SB_DFFESS.$proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:742$196'. Removing empty process `SB_DFFESS.$proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:742$196'. Removing empty process `SB_DFFER.$proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:0$195'. Found and cleaned up 1 empty switch in `\SB_DFFER.$proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:662$192'. Removing empty process `SB_DFFER.$proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:662$192'. Removing empty process `SB_DFFESR.$proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:0$191'. Found and cleaned up 2 empty switches in `\SB_DFFESR.$proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:601$185'. Removing empty process `SB_DFFESR.$proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:601$185'. Removing empty process `SB_DFFS.$proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:0$184'. Removing empty process `SB_DFFS.$proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:527$182'. Removing empty process `SB_DFFSS.$proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:0$181'. Found and cleaned up 1 empty switch in `\SB_DFFSS.$proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:477$179'. Removing empty process `SB_DFFSS.$proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:477$179'. Removing empty process `SB_DFFR.$proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:0$178'. Removing empty process `SB_DFFR.$proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:406$176'. Removing empty process `SB_DFFSR.$proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:0$175'. Found and cleaned up 1 empty switch in `\SB_DFFSR.$proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:356$173'. Removing empty process `SB_DFFSR.$proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:356$173'. Removing empty process `SB_DFFE.$proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:0$172'. Found and cleaned up 1 empty switch in `\SB_DFFE.$proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:311$171'. Removing empty process `SB_DFFE.$proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:311$171'. Removing empty process `SB_DFF.$proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:0$170'. Removing empty process `SB_DFF.$proc$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:271$169'. Removing empty process `top.$group_46'. Removing empty process `top.$group_45'. Removing empty process `top.$group_44'. Removing empty process `top.$group_43'. Removing empty process `top.$group_42'. Removing empty process `top.$group_41'. Removing empty process `top.$group_40'. Removing empty process `top.$group_39'. Removing empty process `top.$group_38'. Removing empty process `top.$group_37'. Removing empty process `top.$group_36'. Removing empty process `top.$group_35'. Removing empty process `top.$group_34'. Removing empty process `top.$group_33'. Removing empty process `top.$group_32'. Removing empty process `top.$group_31'. Removing empty process `top.$group_30'. Removing empty process `top.$group_29'. Removing empty process `top.$group_28'. Removing empty process `top.$group_27'. Removing empty process `top.$group_26'. Removing empty process `top.$group_25'. Removing empty process `top.$group_24'. Removing empty process `top.$group_23'. Removing empty process `top.$group_22'. Removing empty process `top.$group_21'. Removing empty process `top.$group_20'. Removing empty process `top.$group_19'. Removing empty process `top.$group_18'. Removing empty process `top.$group_17'. Removing empty process `top.$group_16'. Removing empty process `top.$group_48'. Removing empty process `top.$group_14'. Removing empty process `top.$group_13'. Removing empty process `top.$group_12'. Removing empty process `top.$group_11'. Removing empty process `top.$group_10'. Removing empty process `top.$group_9'. Removing empty process `top.$group_8'. Removing empty process `top.$group_47'. Removing empty process `top.$group_6'. Removing empty process `top.$group_5'. Removing empty process `top.$group_4'. Removing empty process `top.$group_3'. Removing empty process `top.$group_2'. Removing empty process `top.$group_1'. Removing empty process `top.$group_0'. Removing empty process `top.cd_sync.$group_4'. Removing empty process `top.cd_sync.$group_3'. Found and cleaned up 1 empty switch in `\top.cd_sync.$group_2'. Removing empty process `top.cd_sync.$group_2'. Found and cleaned up 1 empty switch in `\top.cd_sync.$group_1'. Removing empty process `top.cd_sync.$group_1'. Removing empty process `top.cd_sync.$group_0'. Found and cleaned up 2 empty switches in `\top.serial.$group_11'. Removing empty process `top.serial.$group_11'. Found and cleaned up 3 empty switches in `\top.serial.$group_10'. Removing empty process `top.serial.$group_10'. Found and cleaned up 3 empty switches in `\top.serial.$group_9'. Removing empty process `top.serial.$group_9'. Found and cleaned up 2 empty switches in `\top.serial.$group_8'. Removing empty process `top.serial.$group_8'. Found and cleaned up 2 empty switches in `\top.serial.$group_7'. Removing empty process `top.serial.$group_7'. Found and cleaned up 2 empty switches in `\top.serial.$group_6'. Removing empty process `top.serial.$group_6'. Found and cleaned up 3 empty switches in `\top.serial.$group_5'. Removing empty process `top.serial.$group_5'. Found and cleaned up 1 empty switch in `\top.serial.$group_4'. Removing empty process `top.serial.$group_4'. Found and cleaned up 1 empty switch in `\top.serial.$group_3'. Removing empty process `top.serial.$group_3'. Removing empty process `top.serial.$group_2'. Removing empty process `top.serial.$group_1'. Removing empty process `top.serial.$group_0'. Found and cleaned up 3 empty switches in `\top.serial.ser_internal.$group_11'. Removing empty process `top.serial.ser_internal.$group_11'. Found and cleaned up 5 empty switches in `\top.serial.ser_internal.$group_10'. Removing empty process `top.serial.ser_internal.$group_10'. Found and cleaned up 5 empty switches in `\top.serial.ser_internal.$group_9'. Removing empty process `top.serial.ser_internal.$group_9'. Found and cleaned up 4 empty switches in `\top.serial.ser_internal.$group_8'. Removing empty process `top.serial.ser_internal.$group_8'. Found and cleaned up 7 empty switches in `\top.serial.ser_internal.$group_7'. Removing empty process `top.serial.ser_internal.$group_7'. Found and cleaned up 1 empty switch in `\top.serial.ser_internal.$group_6'. Removing empty process `top.serial.ser_internal.$group_6'. Removing empty process `top.serial.ser_internal.$group_5'. Found and cleaned up 4 empty switches in `\top.serial.ser_internal.$group_4'. Removing empty process `top.serial.ser_internal.$group_4'. Found and cleaned up 4 empty switches in `\top.serial.ser_internal.$group_3'. Removing empty process `top.serial.ser_internal.$group_3'. Found and cleaned up 4 empty switches in `\top.serial.ser_internal.$group_2'. Removing empty process `top.serial.ser_internal.$group_2'. Found and cleaned up 1 empty switch in `\top.serial.ser_internal.$group_1'. Removing empty process `top.serial.ser_internal.$group_1'. Removing empty process `top.serial.ser_internal.$group_0'. Found and cleaned up 2 empty switches in `\top.timer.$group_3'. Removing empty process `top.timer.$group_3'. Found and cleaned up 3 empty switches in `\top.timer.$group_2'. Removing empty process `top.timer.$group_2'. Removing empty process `top.timer.$group_1'. Found and cleaned up 4 empty switches in `\top.timer.$group_0'. Removing empty process `top.timer.$group_0'. Found and cleaned up 1 empty switch in `\top.decoder.$group_23'. Removing empty process `top.decoder.$group_23'. Found and cleaned up 1 empty switch in `\top.decoder.$group_22'. Removing empty process `top.decoder.$group_22'. Found and cleaned up 1 empty switch in `\top.decoder.$group_21'. Removing empty process `top.decoder.$group_21'. Found and cleaned up 1 empty switch in `\top.decoder.$group_20'. Removing empty process `top.decoder.$group_20'. Removing empty process `top.decoder.$group_19'. Removing empty process `top.decoder.$group_18'. Removing empty process `top.decoder.$group_17'. Removing empty process `top.decoder.$group_16'. Removing empty process `top.decoder.$group_25'. Removing empty process `top.decoder.$group_14'. Removing empty process `top.decoder.$group_13'. Removing empty process `top.decoder.$group_12'. Removing empty process `top.decoder.$group_11'. Found and cleaned up 1 empty switch in `\top.decoder.$group_24'. Removing empty process `top.decoder.$group_24'. Removing empty process `top.decoder.$group_9'. Removing empty process `top.decoder.$group_8'. Removing empty process `top.decoder.$group_7'. Removing empty process `top.decoder.$group_6'. Removing empty process `top.decoder.$group_5'. Removing empty process `top.decoder.$group_4'. Removing empty process `top.decoder.$group_3'. Removing empty process `top.decoder.$group_2'. Removing empty process `top.decoder.$group_1'. Removing empty process `top.decoder.$group_0'. Found and cleaned up 2 empty switches in `\top.leds.$group_2'. Removing empty process `top.leds.$group_2'. Found and cleaned up 2 empty switches in `\top.leds.$group_1'. Removing empty process `top.leds.$group_1'. Found and cleaned up 2 empty switches in `\top.leds.$group_0'. Removing empty process `top.leds.$group_0'. Found and cleaned up 2 empty switches in `\top.mem.$group_6'. Removing empty process `top.mem.$group_6'. Found and cleaned up 1 empty switch in `\top.mem.$group_5'. Removing empty process `top.mem.$group_5'. Removing empty process `top.mem.$group_4'. Removing empty process `top.mem.$group_3'. Removing empty process `top.mem.$group_2'. Removing empty process `top.mem.$group_1'. Removing empty process `top.mem.$group_0'. Removing empty process `top.cpu.$group_49'. Removing empty process `top.cpu.$group_48'. Removing empty process `top.cpu.$group_47'. Removing empty process `top.cpu.$group_46'. Removing empty process `top.cpu.$group_45'. Removing empty process `top.cpu.$group_44'. Removing empty process `top.cpu.$group_43'. Removing empty process `top.cpu.$group_42'. Found and cleaned up 1 empty switch in `\top.cpu.$group_41'. Removing empty process `top.cpu.$group_41'. Found and cleaned up 1 empty switch in `\top.cpu.$group_40'. Removing empty process `top.cpu.$group_40'. Found and cleaned up 1 empty switch in `\top.cpu.$group_39'. Removing empty process `top.cpu.$group_39'. Found and cleaned up 2 empty switches in `\top.cpu.$group_38'. Removing empty process `top.cpu.$group_38'. Removing empty process `top.cpu.$group_37'. Removing empty process `top.cpu.$group_36'. Found and cleaned up 5 empty switches in `\top.cpu.$group_35'. Removing empty process `top.cpu.$group_35'. Found and cleaned up 2 empty switches in `\top.cpu.$group_34'. Removing empty process `top.cpu.$group_34'. Found and cleaned up 2 empty switches in `\top.cpu.$group_33'. Removing empty process `top.cpu.$group_33'. Removing empty process `top.cpu.$group_32'. Removing empty process `top.cpu.$group_31'. Removing empty process `top.cpu.$group_30'. Removing empty process `top.cpu.$group_29'. Removing empty process `top.cpu.$group_28'. Removing empty process `top.cpu.$group_27'. Removing empty process `top.cpu.$group_26'. Found and cleaned up 5 empty switches in `\top.cpu.$group_25'. Removing empty process `top.cpu.$group_25'. Removing empty process `top.cpu.$group_24'. Removing empty process `top.cpu.$group_23'. Removing empty process `top.cpu.$group_22'. Removing empty process `top.cpu.$group_21'. Removing empty process `top.cpu.$group_20'. Removing empty process `top.cpu.$group_19'. Removing empty process `top.cpu.$group_18'. Removing empty process `top.cpu.$group_17'. Removing empty process `top.cpu.$group_16'. Removing empty process `top.cpu.$group_15'. Removing empty process `top.cpu.$group_14'. Removing empty process `top.cpu.$group_13'. Removing empty process `top.cpu.$group_12'. Found and cleaned up 5 empty switches in `\top.cpu.$group_11'. Removing empty process `top.cpu.$group_11'. Found and cleaned up 6 empty switches in `\top.cpu.$group_10'. Removing empty process `top.cpu.$group_10'. Found and cleaned up 3 empty switches in `\top.cpu.$group_9'. Removing empty process `top.cpu.$group_9'. Removing empty process `top.cpu.$group_8'. Removing empty process `top.cpu.$group_7'. Removing empty process `top.cpu.$group_6'. Removing empty process `top.cpu.$group_5'. Removing empty process `top.cpu.$group_4'. Removing empty process `top.cpu.$group_3'. Removing empty process `top.cpu.$group_2'. Removing empty process `top.cpu.$group_1'. Removing empty process `top.cpu.$group_0'. Found and cleaned up 7 empty switches in `\top.cpu.exception_router.$group_3'. Removing empty process `top.cpu.exception_router.$group_3'. Found and cleaned up 6 empty switches in `\top.cpu.exception_router.$group_2'. Removing empty process `top.cpu.exception_router.$group_2'. Removing empty process `top.cpu.exception_router.$group_1'. Removing empty process `top.cpu.exception_router.$group_0'. Found and cleaned up 1 empty switch in `\top.cpu.decode.$group_21'. Removing empty process `top.cpu.decode.$group_21'. Found and cleaned up 1 empty switch in `\top.cpu.decode.$group_20'. Removing empty process `top.cpu.decode.$group_20'. Found and cleaned up 4 empty switches in `\top.cpu.decode.$group_19'. Removing empty process `top.cpu.decode.$group_19'. Found and cleaned up 11 empty switches in `\top.cpu.decode.$group_18'. Removing empty process `top.cpu.decode.$group_18'. Found and cleaned up 3 empty switches in `\top.cpu.decode.$group_17'. Removing empty process `top.cpu.decode.$group_17'. Found and cleaned up 2 empty switches in `\top.cpu.decode.$group_16'. Removing empty process `top.cpu.decode.$group_16'. Found and cleaned up 2 empty switches in `\top.cpu.decode.$group_15'. Removing empty process `top.cpu.decode.$group_15'. Found and cleaned up 2 empty switches in `\top.cpu.decode.$group_14'. Removing empty process `top.cpu.decode.$group_14'. Found and cleaned up 1 empty switch in `\top.cpu.decode.$group_13'. Removing empty process `top.cpu.decode.$group_13'. Found and cleaned up 1 empty switch in `\top.cpu.decode.$group_12'. Removing empty process `top.cpu.decode.$group_12'. Found and cleaned up 1 empty switch in `\top.cpu.decode.$group_11'. Removing empty process `top.cpu.decode.$group_11'. Found and cleaned up 23 empty switches in `\top.cpu.decode.$group_10'. Removing empty process `top.cpu.decode.$group_10'. Found and cleaned up 6 empty switches in `\top.cpu.decode.$group_9'. Removing empty process `top.cpu.decode.$group_9'. Found and cleaned up 4 empty switches in `\top.cpu.decode.$group_8'. Removing empty process `top.cpu.decode.$group_8'. Found and cleaned up 2 empty switches in `\top.cpu.decode.$group_7'. Removing empty process `top.cpu.decode.$group_7'. Removing empty process `top.cpu.decode.$group_6'. Removing empty process `top.cpu.decode.$group_5'. Removing empty process `top.cpu.decode.$group_4'. Removing empty process `top.cpu.decode.$group_3'. Removing empty process `top.cpu.decode.$group_2'. Removing empty process `top.cpu.decode.$group_1'. Removing empty process `top.cpu.decode.$group_0'. Removing empty process `top.cpu.datapath.$group_26'. Removing empty process `top.cpu.datapath.$group_25'. Removing empty process `top.cpu.datapath.$group_24'. Removing empty process `top.cpu.datapath.$group_23'. Removing empty process `top.cpu.datapath.$group_22'. Removing empty process `top.cpu.datapath.$group_21'. Removing empty process `top.cpu.datapath.$group_20'. Removing empty process `top.cpu.datapath.$group_19'. Removing empty process `top.cpu.datapath.$group_18'. Removing empty process `top.cpu.datapath.$group_17'. Removing empty process `top.cpu.datapath.$group_16'. Removing empty process `top.cpu.datapath.$group_15'. Removing empty process `top.cpu.datapath.$group_14'. Removing empty process `top.cpu.datapath.$group_13'. Removing empty process `top.cpu.datapath.$group_12'. Removing empty process `top.cpu.datapath.$group_11'. Removing empty process `top.cpu.datapath.$group_10'. Removing empty process `top.cpu.datapath.$group_9'. Removing empty process `top.cpu.datapath.$group_8'. Removing empty process `top.cpu.datapath.$group_7'. Removing empty process `top.cpu.datapath.$group_6'. Removing empty process `top.cpu.datapath.$group_5'. Removing empty process `top.cpu.datapath.$group_4'. Removing empty process `top.cpu.datapath.$group_3'. Removing empty process `top.cpu.datapath.$group_2'. Removing empty process `top.cpu.datapath.$group_1'. Removing empty process `top.cpu.datapath.$group_0'. Removing empty process `top.cpu.datapath.csrfile.$group_11'. Found and cleaned up 1 empty switch in `\top.cpu.datapath.csrfile.$group_10'. Removing empty process `top.cpu.datapath.csrfile.$group_10'. Found and cleaned up 5 empty switches in `\top.cpu.datapath.csrfile.$group_9'. Removing empty process `top.cpu.datapath.csrfile.$group_9'. Found and cleaned up 3 empty switches in `\top.cpu.datapath.csrfile.$group_8'. Removing empty process `top.cpu.datapath.csrfile.$group_8'. Found and cleaned up 4 empty switches in `\top.cpu.datapath.csrfile.$group_7'. Removing empty process `top.cpu.datapath.csrfile.$group_7'. Removing empty process `top.cpu.datapath.csrfile.$group_6'. Found and cleaned up 1 empty switch in `\top.cpu.datapath.csrfile.$group_5'. Removing empty process `top.cpu.datapath.csrfile.$group_5'. Removing empty process `top.cpu.datapath.csrfile.$group_4'. Found and cleaned up 1 empty switch in `\top.cpu.datapath.csrfile.$group_3'. Removing empty process `top.cpu.datapath.csrfile.$group_3'. Removing empty process `top.cpu.datapath.csrfile.$group_2'. Removing empty process `top.cpu.datapath.csrfile.$group_1'. Removing empty process `top.cpu.datapath.csrfile.$group_0'. Found and cleaned up 1 empty switch in `\top.cpu.datapath.regfile.$group_6'. Removing empty process `top.cpu.datapath.regfile.$group_6'. Found and cleaned up 1 empty switch in `\top.cpu.datapath.regfile.$group_5'. Removing empty process `top.cpu.datapath.regfile.$group_5'. Found and cleaned up 1 empty switch in `\top.cpu.datapath.regfile.$group_4'. Removing empty process `top.cpu.datapath.regfile.$group_4'. Found and cleaned up 1 empty switch in `\top.cpu.datapath.regfile.$group_3'. Removing empty process `top.cpu.datapath.regfile.$group_3'. Found and cleaned up 1 empty switch in `\top.cpu.datapath.regfile.$group_2'. Removing empty process `top.cpu.datapath.regfile.$group_2'. Removing empty process `top.cpu.datapath.regfile.$group_1'. Removing empty process `top.cpu.datapath.regfile.$group_0'. Found and cleaned up 2 empty switches in `\top.cpu.datapath.pc_mod.$group_0'. Removing empty process `top.cpu.datapath.pc_mod.$group_0'. Found and cleaned up 1 empty switch in `\top.cpu.control.$group_33'. Removing empty process `top.cpu.control.$group_33'. Found and cleaned up 1 empty switch in `\top.cpu.control.$group_32'. Removing empty process `top.cpu.control.$group_32'. Removing empty process `top.cpu.control.$group_31'. Removing empty process `top.cpu.control.$group_30'. Removing empty process `top.cpu.control.$group_29'. Removing empty process `top.cpu.control.$group_28'. Removing empty process `top.cpu.control.$group_27'. Removing empty process `top.cpu.control.$group_26'. Removing empty process `top.cpu.control.$group_25'. Removing empty process `top.cpu.control.$group_24'. Removing empty process `top.cpu.control.$group_23'. Removing empty process `top.cpu.control.$group_22'. Removing empty process `top.cpu.control.$group_21'. Removing empty process `top.cpu.control.$group_20'. Removing empty process `top.cpu.control.$group_19'. Removing empty process `top.cpu.control.$group_18'. Removing empty process `top.cpu.control.$group_17'. Removing empty process `top.cpu.control.$group_16'. Removing empty process `top.cpu.control.$group_15'. Removing empty process `top.cpu.control.$group_14'. Removing empty process `top.cpu.control.$group_13'. Removing empty process `top.cpu.control.$group_12'. Removing empty process `top.cpu.control.$group_11'. Removing empty process `top.cpu.control.$group_10'. Removing empty process `top.cpu.control.$group_9'. Removing empty process `top.cpu.control.$group_8'. Removing empty process `top.cpu.control.$group_7'. Removing empty process `top.cpu.control.$group_6'. Removing empty process `top.cpu.control.$group_5'. Removing empty process `top.cpu.control.$group_4'. Removing empty process `top.cpu.control.$group_3'. Removing empty process `top.cpu.control.$group_2'. Removing empty process `top.cpu.control.$group_1'. Removing empty process `top.cpu.control.$group_0'. Found and cleaned up 5 empty switches in `\top.cpu.control.sequencer.$group_2'. Removing empty process `top.cpu.control.sequencer.$group_2'. Found and cleaned up 1 empty switch in `\top.cpu.control.sequencer.$group_1'. Removing empty process `top.cpu.control.sequencer.$group_1'. Found and cleaned up 1 empty switch in `\top.cpu.control.sequencer.$group_0'. Removing empty process `top.cpu.control.sequencer.$group_0'. Removing empty process `top.cpu.control.ucoderom.$group_1'. Removing empty process `top.cpu.control.ucoderom.$group_0'. Removing empty process `top.cpu.alu.$group_20'. Found and cleaned up 2 empty switches in `\top.cpu.alu.$group_19'. Removing empty process `top.cpu.alu.$group_19'. Found and cleaned up 1 empty switch in `\top.cpu.alu.$group_18'. Removing empty process `top.cpu.alu.$group_18'. Removing empty process `top.cpu.alu.$group_17'. Removing empty process `top.cpu.alu.$group_16'. Removing empty process `top.cpu.alu.$group_15'. Removing empty process `top.cpu.alu.$group_14'. Removing empty process `top.cpu.alu.$group_13'. Removing empty process `top.cpu.alu.$group_12'. Removing empty process `top.cpu.alu.$group_11'. Removing empty process `top.cpu.alu.$group_10'. Removing empty process `top.cpu.alu.$group_9'. Removing empty process `top.cpu.alu.$group_8'. Removing empty process `top.cpu.alu.$group_7'. Removing empty process `top.cpu.alu.$group_6'. Removing empty process `top.cpu.alu.$group_5'. Removing empty process `top.cpu.alu.$group_4'. Removing empty process `top.cpu.alu.$group_3'. Removing empty process `top.cpu.alu.$group_2'. Found and cleaned up 1 empty switch in `\top.cpu.alu.$group_1'. Removing empty process `top.cpu.alu.$group_1'. Found and cleaned up 1 empty switch in `\top.cpu.alu.$group_0'. Removing empty process `top.cpu.alu.$group_0'. Removing empty process `top.cpu.alu.sal.$group_0'. Removing empty process `top.cpu.alu.srl.$group_0'. Removing empty process `top.cpu.alu.sll.$group_0'. Removing empty process `top.cpu.alu.xor.$group_0'. Removing empty process `top.cpu.alu.or_.$group_0'. Removing empty process `top.cpu.alu.and_.$group_0'. Removing empty process `top.cpu.alu.sub.$group_0'. Removing empty process `top.cpu.alu.add.$group_0'. Cleaned up 246 empty switches. 2.3.12. Executing OPT_EXPR pass (perform const folding). Optimizing module top. Optimizing module top.pin_clk12_0. Optimizing module top.pin_inp_0. Optimizing module top.pin_uart_0__dcd. Optimizing module top.pin_uart_0__dsr. Optimizing module top.pin_uart_0__dtr. Optimizing module top.pin_uart_0__cts. Optimizing module top.pin_uart_0__rts. Optimizing module top.pin_uart_0__tx. Optimizing module top.pin_uart_0__rx. Optimizing module top.pin_led_4. Optimizing module top.pin_led_3. Optimizing module top.pin_led_2. Optimizing module top.pin_led_1. Optimizing module top.pin_led_0. Optimizing module top.cd_sync. Optimizing module top.serial. Optimizing module top.serial.ser_internal. Optimizing module top.timer. Optimizing module top.decoder. Optimizing module top.leds. Optimizing module top.mem. Optimizing module top.cpu. Optimizing module top.cpu.exception_router. Optimizing module top.cpu.decode. Optimizing module top.cpu.datapath. Optimizing module top.cpu.datapath.csrfile. Optimizing module top.cpu.datapath.regfile. Optimizing module top.cpu.datapath.pc_mod. Optimizing module top.cpu.control. Optimizing module top.cpu.control.sequencer. Optimizing module top.cpu.control.ucoderom. Optimizing module top.cpu.alu. Optimizing module top.cpu.alu.sal. Optimizing module top.cpu.alu.srl. Optimizing module top.cpu.alu.sll. Optimizing module top.cpu.alu.xor. Optimizing module top.cpu.alu.or_. Optimizing module top.cpu.alu.and_. Optimizing module top.cpu.alu.sub. Optimizing module top.cpu.alu.add. 2.4. Executing FLATTEN pass (flatten design). Deleting now unused module top.pin_clk12_0. Deleting now unused module top.pin_inp_0. Deleting now unused module top.pin_uart_0__dcd. Deleting now unused module top.pin_uart_0__dsr. Deleting now unused module top.pin_uart_0__dtr. Deleting now unused module top.pin_uart_0__cts. Deleting now unused module top.pin_uart_0__rts. Deleting now unused module top.pin_uart_0__tx. Deleting now unused module top.pin_uart_0__rx. Deleting now unused module top.pin_led_4. Deleting now unused module top.pin_led_3. Deleting now unused module top.pin_led_2. Deleting now unused module top.pin_led_1. Deleting now unused module top.pin_led_0. Deleting now unused module top.cd_sync. Deleting now unused module top.serial. Deleting now unused module top.serial.ser_internal. Deleting now unused module top.timer. Deleting now unused module top.decoder. Deleting now unused module top.leds. Deleting now unused module top.mem. Deleting now unused module top.cpu. Deleting now unused module top.cpu.exception_router. Deleting now unused module top.cpu.decode. Deleting now unused module top.cpu.datapath. Deleting now unused module top.cpu.datapath.csrfile. Deleting now unused module top.cpu.datapath.regfile. Deleting now unused module top.cpu.datapath.pc_mod. Deleting now unused module top.cpu.control. Deleting now unused module top.cpu.control.sequencer. Deleting now unused module top.cpu.control.ucoderom. Deleting now unused module top.cpu.alu. Deleting now unused module top.cpu.alu.sal. Deleting now unused module top.cpu.alu.srl. Deleting now unused module top.cpu.alu.sll. Deleting now unused module top.cpu.alu.xor. Deleting now unused module top.cpu.alu.or_. Deleting now unused module top.cpu.alu.and_. Deleting now unused module top.cpu.alu.sub. Deleting now unused module top.cpu.alu.add. 2.5. Executing TRIBUF pass. 2.6. Executing DEMINOUT pass (demote inout ports to input or output). 2.7. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 2.8. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 36 unused cells and 534 unused wires. 2.9. Executing CHECK pass (checking for obvious problems). Checking module top... Found and reported 0 problems. 2.10. Executing OPT pass (performing simple optimizations). 2.10.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 2.10.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 212 cells. 2.10.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. dead port 3/3 on $pmux $flatten\cpu.$procmux$740. dead port 2/2 on $mux $flatten\cpu.$procmux$750. dead port 2/2 on $mux $flatten\cpu.$procmux$752. Removed 3 multiplexer ports. 2.10.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. New ctrl vector for $pmux cell $flatten\cpu.\decode.$procmux$1032: $auto$opt_reduce.cc:134:opt_pmux$1254 New ctrl vector for $pmux cell $flatten\cpu.\decode.$procmux$841: $auto$opt_reduce.cc:134:opt_pmux$1256 New ctrl vector for $pmux cell $flatten\cpu.\decode.$procmux$916: { $auto$opt_reduce.cc:134:opt_pmux$1260 $flatten\cpu.\decode.$procmux$869_CMP $flatten\cpu.\decode.$procmux$867_CMP $auto$opt_reduce.cc:134:opt_pmux$1258 $flatten\cpu.\decode.$procmux$865_CMP } New ctrl vector for $pmux cell $flatten\cpu.\decode.$procmux$960: { $flatten\cpu.\decode.$procmux$878_CMP $flatten\cpu.\decode.$procmux$872_CMP $auto$opt_reduce.cc:134:opt_pmux$1262 $flatten\cpu.\decode.$procmux$868_CMP $flatten\cpu.\decode.$procmux$867_CMP $flatten\cpu.\decode.$procmux$866_CMP $flatten\cpu.\decode.$procmux$865_CMP $flatten\cpu.\decode.$procmux$864_CMP $flatten\cpu.\decode.$procmux$1024_CMP } Optimizing cells in module \top. Performed a total of 4 changes. 2.10.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 5 cells. 2.10.6. Executing OPT_DFF pass (perform DFF optimizations). 2.10.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 0 unused cells and 219 unused wires. 2.10.8. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 2.10.9. Rerunning OPT passes. (Maybe there is more to do..) 2.10.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 2.10.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. New ctrl vector for $pmux cell $flatten\cpu.\decode.$procmux$960: { $flatten\cpu.\decode.$procmux$878_CMP $flatten\cpu.\decode.$procmux$872_CMP $auto$opt_reduce.cc:134:opt_pmux$1262 $flatten\cpu.\decode.$procmux$867_CMP $flatten\cpu.\decode.$procmux$866_CMP $flatten\cpu.\decode.$procmux$865_CMP $auto$opt_reduce.cc:134:opt_pmux$1264 $flatten\cpu.\decode.$procmux$1024_CMP } Optimizing cells in module \top. Performed a total of 1 changes. 2.10.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 2.10.13. Executing OPT_DFF pass (perform DFF optimizations). 2.10.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 2.10.15. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 2.10.16. Rerunning OPT passes. (Maybe there is more to do..) 2.10.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 2.10.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 2.10.19. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 2.10.20. Executing OPT_DFF pass (perform DFF optimizations). 2.10.21. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 2.10.22. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 2.10.23. Finished OPT passes. (There is nothing left to do.) 2.11. Executing FSM pass (extract and optimize FSM). 2.11.1. Executing FSM_DETECT pass (finding FSMs in design). Not marking top.cpu.decode.e_type as FSM state register: Users of register don't seem to benefit from recoding. Register has an initialization value. 2.11.2. Executing FSM_EXTRACT pass (extracting FSM from design). 2.11.3. Executing FSM_OPT pass (simple optimizations of FSMs). 2.11.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 2.11.5. Executing FSM_OPT pass (simple optimizations of FSMs). 2.11.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). 2.11.7. Executing FSM_INFO pass (dumping all available information on FSM cells). 2.11.8. Executing FSM_MAP pass (mapping FSMs to basic logic). 2.12. Executing OPT pass (performing simple optimizations). 2.12.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 2.12.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 2.12.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 2.12.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 2.12.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 2.12.6. Executing OPT_DFF pass (perform DFF optimizations). Adding SRST signal on $flatten\timer.$30 ($dff) from module top (D = $flatten\timer.$procmux$573_Y, Q = \timer.bus__ack, rval = 1'0). Adding SRST signal on $flatten\timer.$29 ($dff) from module top (D = $flatten\timer.$procmux$579_Y, Q = \timer.bus__dat_r, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$1266 ($sdff) from module top (D = { 31'0000000000000000000000000000000 \timer.prescalar [14] }, Q = \timer.bus__dat_r). Adding SRST signal on $flatten\timer.$28 ($dff) from module top (D = { $flatten\timer.$procmux$587_Y $flatten\timer.$1 [13:0] }, Q = \timer.prescalar, rval = 15'000000000000000). Adding SRST signal on $flatten\serial.\ser_internal.$86 ($dff) from module top (D = $flatten\serial.\ser_internal.$procmux$485_Y, Q = \serial.ser_internal.rx_shreg, rval = 10'1111111111). Adding EN signal on $auto$ff.cc:266:slice$1271 ($sdff) from module top (D = { \pin_uart_0__rx.uart_0__rx__i \serial.ser_internal.rx_shreg [9:1] }, Q = \serial.ser_internal.rx_shreg). Adding SRST signal on $flatten\serial.\ser_internal.$85 ($dff) from module top (D = $flatten\serial.\ser_internal.$procmux$497_Y, Q = \serial.ser_internal.rx_phase, rval = 11'00000000000). Adding EN signal on $auto$ff.cc:266:slice$1279 ($sdff) from module top (D = $flatten\serial.\ser_internal.$procmux$497_Y, Q = \serial.ser_internal.rx_phase). Adding SRST signal on $flatten\serial.\ser_internal.$84 ($dff) from module top (D = $flatten\serial.\ser_internal.$procmux$509_Y, Q = \serial.ser_internal.rx_count, rval = 4'0000). Adding EN signal on $auto$ff.cc:266:slice$1287 ($sdff) from module top (D = $flatten\serial.\ser_internal.$procmux$509_Y, Q = \serial.ser_internal.rx_count). Adding SRST signal on $flatten\serial.\ser_internal.$82 ($dff) from module top (D = $flatten\serial.\ser_internal.$procmux$534_Y, Q = \serial.ser_internal.rx_rdy, rval = 1'0). Adding EN signal on $auto$ff.cc:266:slice$1297 ($sdff) from module top (D = $flatten\serial.\ser_internal.$procmux$534_Y, Q = \serial.ser_internal.rx_rdy). Adding SRST signal on $flatten\serial.\ser_internal.$81 ($dff) from module top (D = $flatten\serial.\ser_internal.$procmux$546_Y, Q = \serial.ser_internal.tx_phase, rval = 11'00000000000). Adding EN signal on $auto$ff.cc:266:slice$1309 ($sdff) from module top (D = $flatten\serial.\ser_internal.$procmux$546_Y, Q = \serial.ser_internal.tx_phase). Adding SRST signal on $flatten\serial.\ser_internal.$80 ($dff) from module top (D = $flatten\serial.\ser_internal.$procmux$556_Y, Q = \serial.ser_internal.tx_count, rval = 4'0000). Adding EN signal on $auto$ff.cc:266:slice$1313 ($sdff) from module top (D = $flatten\serial.\ser_internal.$procmux$556_Y, Q = \serial.ser_internal.tx_count). Adding SRST signal on $flatten\serial.\ser_internal.$79 ($dff) from module top (D = $flatten\serial.\ser_internal.$procmux$566_Y, Q = \serial.ser_internal.tx_shreg, rval = 10'1111111111). Adding EN signal on $auto$ff.cc:266:slice$1321 ($sdff) from module top (D = $flatten\serial.\ser_internal.$procmux$566_Y, Q = \serial.ser_internal.tx_shreg). Adding SRST signal on $flatten\serial.$82 ($dff) from module top (D = $flatten\serial.$procmux$435_Y, Q = \serial.bus__ack, rval = 1'0). Adding SRST signal on $flatten\serial.$81 ($dff) from module top (D = $flatten\serial.$procmux$441_Y, Q = \serial.tx_ack_irq, rval = 1'0). Adding EN signal on $auto$ff.cc:266:slice$1330 ($sdff) from module top (D = $flatten\serial.$procmux$441_Y, Q = \serial.tx_ack_irq). Adding SRST signal on $flatten\serial.$80 ($dff) from module top (D = $flatten\serial.$procmux$447_Y, Q = \serial.rx_rdy_irq, rval = 1'0). Adding EN signal on $auto$ff.cc:266:slice$1334 ($sdff) from module top (D = $flatten\serial.$procmux$447_Y, Q = \serial.rx_rdy_irq). Adding SRST signal on $flatten\serial.$79 ($dff) from module top (D = { $flatten\serial.$procmux$463_Y $flatten\serial.$procmux$473_Y $flatten\serial.$procmux$467_Y }, Q = \serial.bus__dat_r, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$1338 ($sdff) from module top (D = { 22'0000000000000000000000 \serial.ser_internal.rx_shreg [8:1] }, Q = { \serial.bus__dat_r [31:10] \serial.bus__dat_r [7:0] }). Adding EN signal on $auto$ff.cc:266:slice$1338 ($sdff) from module top (D = $flatten\serial.$procmux$473_Y, Q = \serial.bus__dat_r [9:8]). Adding SRST signal on $flatten\serial.$78 ($dff) from module top (D = \serial.ser_internal_tx_ack, Q = \serial.tx_ack_prev, rval = 1'0). Adding SRST signal on $flatten\serial.$77 ($dff) from module top (D = \serial.ser_internal.rx_rdy, Q = \serial.rx_rdy_prev, rval = 1'0). Adding SRST signal on $flatten\mem.$17 ($dff) from module top (D = $flatten\mem.$procmux$620_Y, Q = \mem.bus__ack, rval = 1'0). Adding SRST signal on $flatten\leds.$29 ($dff) from module top (D = $flatten\leds.$procmux$607_Y, Q = \leds.bus__ack, rval = 1'0). Adding SRST signal on $flatten\leds.$28 ($dff) from module top (D = $flatten\leds.$procmux$611_Y, Q = \leds.bus__dat_r, rval = 8'00000000). Adding EN signal on $auto$ff.cc:266:slice$1347 ($sdff) from module top (D = { 6'000000 \leds.inp [1:0] }, Q = \leds.bus__dat_r). Adding SRST signal on $flatten\leds.$27 ($dff) from module top (D = $flatten\leds.$procmux$615_Y, Q = \leds.leds, rval = 8'00000000). Adding EN signal on $auto$ff.cc:266:slice$1349 ($sdff) from module top (D = \cpu.write_data [7:0], Q = \leds.leds). Adding SRST signal on $flatten\cpu.\exception_router.$101 ($dff) from module top (D = { $flatten\cpu.\exception_router.$procmux$794_Y $flatten\cpu.\exception_router.$procmux$814_Y }, Q = \cpu.exception_router.mcause_latch, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$1351 ($sdff) from module top (D = 1'1, Q = \cpu.exception_router.mcause_latch [31]). Adding EN signal on $auto$ff.cc:266:slice$1351 ($sdff) from module top (D = $flatten\cpu.\exception_router.$procmux$814_Y, Q = \cpu.exception_router.mcause_latch [30:0]). Adding SRST signal on $flatten\cpu.\decode.$289 ($dff) from module top (D = $flatten\cpu.\decode.$procmux$846_Y, Q = \cpu.decode.csr_encoding, rval = 4'0000). Adding EN signal on $auto$ff.cc:266:slice$1368 ($sdff) from module top (D = { \cpu.bus__dat_r [26] \cpu.bus__dat_r [22:20] }, Q = \cpu.decode.csr_encoding). Adding SRST signal on $flatten\cpu.\decode.$288 ($dff) from module top (D = $flatten\cpu.\decode.$procmux$912_Y, Q = \cpu.decode.requested_op, rval = 8'00000000). Adding SRST signal on $flatten\cpu.\decode.$287 ($dff) from module top (D = $flatten\cpu.\decode.$procmux$925_Y, Q = \cpu.decode.imm, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$1375 ($sdff) from module top (D = $flatten\cpu.\decode.$procmux$916_Y, Q = \cpu.decode.imm). Adding SRST signal on $flatten\cpu.\decode.$286 ($dff) from module top (D = $flatten\cpu.\decode.$procmux$929_Y, Q = \cpu.decode.dst, rval = 5'00000). Adding EN signal on $auto$ff.cc:266:slice$1381 ($sdff) from module top (D = \cpu.bus__dat_r [11:7], Q = \cpu.decode.dst). Adding SRST signal on $flatten\cpu.\decode.$285 ($dff) from module top (D = $flatten\cpu.\decode.$procmux$933_Y, Q = \cpu.decode.src_b, rval = 5'00000). Adding EN signal on $auto$ff.cc:266:slice$1383 ($sdff) from module top (D = \cpu.bus__dat_r [24:20], Q = \cpu.decode.src_b). Adding SRST signal on $flatten\cpu.\decode.$284 ($dff) from module top (D = $flatten\cpu.\decode.$procmux$937_Y, Q = \cpu.decode.src_a, rval = 5'00000). Adding EN signal on $auto$ff.cc:266:slice$1385 ($sdff) from module top (D = \cpu.bus__dat_r [19:15], Q = \cpu.decode.src_a). Adding SRST signal on $flatten\cpu.\decode.$283 ($dff) from module top (D = $flatten\cpu.\decode.$145, Q = \cpu.decode.csr_ro_space, rval = 1'0). Adding SRST signal on $flatten\cpu.\decode.$282 ($dff) from module top (D = \cpu.bus__dat_r [14:12], Q = \cpu.decode.csr_op, rval = 3'000). Adding SRST signal on $flatten\cpu.\decode.$281 ($dff) from module top (D = \cpu.bus__dat_r [29:28], Q = \cpu.decode.csr_quadrant, rval = 2'00). Adding SRST signal on $flatten\cpu.\decode.$280 ($dff) from module top (D = $flatten\cpu.\decode.$procmux$1013_Y, Q = \cpu.decode.exception, rval = 1'0). Adding SRST signal on $flatten\cpu.\decode.$279 ($dff) from module top (D = { $flatten\cpu.\decode.$procmux$1017_Y [30:4] $flatten\cpu.\decode.$procmux$1017_Y [2] }, Q = { \cpu.decode.e_type [30:4] \cpu.decode.e_type [2] }, rval = 28'0000000000000000000000000000). Adding SRST signal on $flatten\cpu.\decode.$279 ($dff) from module top (D = { $flatten\cpu.\decode.$procmux$1019_Y [3] $flatten\cpu.\decode.$procmux$1019_Y [0] }, Q = { \cpu.decode.e_type [3] \cpu.decode.e_type [0] }, rval = 2'00). Adding SRST signal on $flatten\cpu.\decode.$279 ($dff) from module top (D = $flatten\cpu.\decode.$procmux$1027_Y [1], Q = \cpu.decode.e_type [1], rval = 1'0). Adding SRST signal on $flatten\cpu.\decode.$278 ($dff) from module top (D = $flatten\cpu.\decode.$procmux$1032_Y, Q = \cpu.decode.forward_csr, rval = 1'0). Adding SRST signal on $flatten\cpu.\decode.$277 ($dff) from module top (D = $flatten\cpu.\decode.$auto$proc_rom.cc:149:do_switch$381, Q = \cpu.decode.csr_map, rval = 2'00). Adding SRST signal on $flatten\cpu.\datapath.\pc_mod.$4 ($dff) from module top (D = $flatten\cpu.\datapath.\pc_mod.$procmux$1178_Y, Q = \cpu.datapath.pc_mod.dat_r, rval = 30'000000000000000000000000000000). Adding EN signal on $auto$ff.cc:266:slice$1418 ($sdff) from module top (D = $flatten\cpu.\datapath.\pc_mod.$procmux$1178_Y, Q = \cpu.datapath.pc_mod.dat_r). Adding SRST signal on $flatten\cpu.\datapath.\csrfile.$42 ($dff) from module top (D = \cpu.datapath.csrfile.pub__adr, Q = \cpu.datapath.csrfile.prev_csr_adr, rval = 5'00000). Adding SRST signal on $flatten\cpu.\datapath.\csrfile.$41 ($dff) from module top (D = { $flatten\cpu.\datapath.\csrfile.$procmux$1052_Y $flatten\cpu.\datapath.\csrfile.$procmux$1102_Y $flatten\cpu.\datapath.\csrfile.$procmux$1112_Y $flatten\cpu.\datapath.\csrfile.$procmux$1062_Y $flatten\cpu.\datapath.\csrfile.$procmux$1122_Y $flatten\cpu.\datapath.\csrfile.$procmux$1072_Y $flatten\cpu.\datapath.\csrfile.$procmux$1082_Y $flatten\cpu.\datapath.\csrfile.$procmux$1092_Y }, Q = \cpu.datapath.csrfile.read_buf, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$1423 ($sdff) from module top (D = { $flatten\cpu.\datapath.\csrfile.$procmux$1050_Y $flatten\cpu.\datapath.\csrfile.$procmux$1100_Y $flatten\cpu.\datapath.\csrfile.$procmux$1110_Y $flatten\cpu.\datapath.\csrfile.$procmux$1060_Y $flatten\cpu.\datapath.\csrfile.$procmux$1120_Y $flatten\cpu.\datapath.\csrfile.$procmux$1070_Y $flatten\cpu.\datapath.\csrfile.$procmux$1080_Y $flatten\cpu.\datapath.\csrfile.$procmux$1090_Y }, Q = \cpu.datapath.csrfile.read_buf). Adding SRST signal on $flatten\cpu.\datapath.\csrfile.$40 ($dff) from module top (D = $flatten\cpu.\datapath.\csrfile.$procmux$1132_Y, Q = \cpu.datapath.csrfile.mie [11], rval = 1'0). Adding EN signal on $flatten\cpu.\datapath.\csrfile.$40 ($dff) from module top (D = 31'0000000000000000000000000000000, Q = { \cpu.datapath.csrfile.mie [31:12] \cpu.datapath.csrfile.mie [10:0] }). Adding EN signal on $auto$ff.cc:266:slice$1429 ($sdff) from module top (D = \cpu.alu.data__o [11], Q = \cpu.datapath.csrfile.mie [11]). Adding SRST signal on $flatten\cpu.\datapath.\csrfile.$39 ($dff) from module top (D = $flatten\cpu.\datapath.\csrfile.$procmux$1144_Y, Q = \cpu.datapath.csrfile.mstatus [3], rval = 1'0). Adding SRST signal on $flatten\cpu.\datapath.\csrfile.$39 ($dff) from module top (D = $flatten\cpu.\datapath.\csrfile.$procmux$1158_Y, Q = \cpu.datapath.csrfile.mstatus [7], rval = 1'0). Adding EN signal on $flatten\cpu.\datapath.\csrfile.$39 ($dff) from module top (D = 30'000000000000000000011000000000, Q = { \cpu.datapath.csrfile.mstatus [31:8] \cpu.datapath.csrfile.mstatus [6:4] \cpu.datapath.csrfile.mstatus [2:0] }). Adding EN signal on $auto$ff.cc:266:slice$1440 ($sdff) from module top (D = $flatten\cpu.\datapath.\csrfile.$procmux$1158_Y, Q = \cpu.datapath.csrfile.mstatus [7]). Adding EN signal on $auto$ff.cc:266:slice$1435 ($sdff) from module top (D = $flatten\cpu.\datapath.\csrfile.$procmux$1144_Y, Q = \cpu.datapath.csrfile.mstatus [3]). Adding SRST signal on $flatten\cpu.\control.\sequencer.$4 ($dff) from module top (D = $flatten\cpu.\control.\sequencer.$1 [7:0], Q = \cpu.control.sequencer.next_adr, rval = 8'00000010). Adding SRST signal on $flatten\cpu.\alu.$25 ($dff) from module top (D = { \cpu.alu.o_mux [31:1] $flatten\cpu.\alu.$procmux$1215_Y }, Q = \cpu.alu.data__o, rval = 0). Adding SRST signal on $flatten\cpu.$72 ($dff) from module top (D = $flatten\cpu.$procmux$664_Y, Q = \cpu.data_adr, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$1459 ($sdff) from module top (D = \cpu.alu.data__o, Q = \cpu.data_adr). Adding SRST signal on $flatten\cpu.$71 ($dff) from module top (D = { $flatten\cpu.$procmux$682_Y $flatten\cpu.$procmux$700_Y $flatten\cpu.$procmux$717_Y $flatten\cpu.$procmux$733_Y }, Q = \cpu.write_data, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$1461 ($sdff) from module top (D = $flatten\cpu.$procmux$686_Y, Q = \cpu.write_data [23:16]). Adding EN signal on $auto$ff.cc:266:slice$1461 ($sdff) from module top (D = $flatten\cpu.$procmux$668_Y, Q = \cpu.write_data [31:24]). Adding EN signal on $auto$ff.cc:266:slice$1461 ($sdff) from module top (D = $flatten\cpu.$procmux$704_Y, Q = \cpu.write_data [15:8]). Adding EN signal on $auto$ff.cc:266:slice$1461 ($sdff) from module top (D = $flatten\cpu.$procmux$721_Y, Q = \cpu.write_data [7:0]). Adding SRST signal on $flatten\cpu.$70 ($dff) from module top (D = $flatten\cpu.$procmux$773_Y, Q = \cpu.b_input, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$1508 ($sdff) from module top (D = $flatten\cpu.$procmux$754_Y, Q = \cpu.b_input). Adding SRST signal on $flatten\cpu.$69 ($dff) from module top (D = $flatten\cpu.$procmux$785_Y, Q = \cpu.a_input, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$1516 ($sdff) from module top (D = $flatten\cpu.$procmux$777_Y, Q = \cpu.a_input). Adding EN signal on $flatten\cd_sync.$11 ($dff) from module top (D = $flatten\cd_sync.$5 [7:0], Q = \cd_sync.timer). Adding EN signal on $flatten\cd_sync.$10 ($dff) from module top (D = 1'1, Q = \cd_sync.ready). Setting constant 0-bit at position 8 on $auto$ff.cc:266:slice$1339 ($sdffe) from module top. Setting constant 0-bit at position 9 on $auto$ff.cc:266:slice$1339 ($sdffe) from module top. Setting constant 0-bit at position 10 on $auto$ff.cc:266:slice$1339 ($sdffe) from module top. Setting constant 0-bit at position 11 on $auto$ff.cc:266:slice$1339 ($sdffe) from module top. Setting constant 0-bit at position 12 on $auto$ff.cc:266:slice$1339 ($sdffe) from module top. Setting constant 0-bit at position 13 on $auto$ff.cc:266:slice$1339 ($sdffe) from module top. Setting constant 0-bit at position 14 on $auto$ff.cc:266:slice$1339 ($sdffe) from module top. Setting constant 0-bit at position 15 on $auto$ff.cc:266:slice$1339 ($sdffe) from module top. Setting constant 0-bit at position 16 on $auto$ff.cc:266:slice$1339 ($sdffe) from module top. Setting constant 0-bit at position 17 on $auto$ff.cc:266:slice$1339 ($sdffe) from module top. Setting constant 0-bit at position 18 on $auto$ff.cc:266:slice$1339 ($sdffe) from module top. Setting constant 0-bit at position 19 on $auto$ff.cc:266:slice$1339 ($sdffe) from module top. Setting constant 0-bit at position 20 on $auto$ff.cc:266:slice$1339 ($sdffe) from module top. Setting constant 0-bit at position 21 on $auto$ff.cc:266:slice$1339 ($sdffe) from module top. Setting constant 0-bit at position 22 on $auto$ff.cc:266:slice$1339 ($sdffe) from module top. Setting constant 0-bit at position 23 on $auto$ff.cc:266:slice$1339 ($sdffe) from module top. Setting constant 0-bit at position 24 on $auto$ff.cc:266:slice$1339 ($sdffe) from module top. Setting constant 0-bit at position 25 on $auto$ff.cc:266:slice$1339 ($sdffe) from module top. Setting constant 0-bit at position 26 on $auto$ff.cc:266:slice$1339 ($sdffe) from module top. Setting constant 0-bit at position 27 on $auto$ff.cc:266:slice$1339 ($sdffe) from module top. Setting constant 0-bit at position 28 on $auto$ff.cc:266:slice$1339 ($sdffe) from module top. Setting constant 0-bit at position 29 on $auto$ff.cc:266:slice$1339 ($sdffe) from module top. Setting constant 0-bit at position 0 on $auto$ff.cc:266:slice$1442 ($dffe) from module top. Setting constant 0-bit at position 1 on $auto$ff.cc:266:slice$1442 ($dffe) from module top. Setting constant 0-bit at position 2 on $auto$ff.cc:266:slice$1442 ($dffe) from module top. Setting constant 0-bit at position 3 on $auto$ff.cc:266:slice$1442 ($dffe) from module top. Setting constant 0-bit at position 4 on $auto$ff.cc:266:slice$1442 ($dffe) from module top. Setting constant 0-bit at position 5 on $auto$ff.cc:266:slice$1442 ($dffe) from module top. Setting constant 0-bit at position 6 on $auto$ff.cc:266:slice$1442 ($dffe) from module top. Setting constant 0-bit at position 7 on $auto$ff.cc:266:slice$1442 ($dffe) from module top. Setting constant 0-bit at position 8 on $auto$ff.cc:266:slice$1442 ($dffe) from module top. Setting constant 1-bit at position 9 on $auto$ff.cc:266:slice$1442 ($dffe) from module top. Setting constant 1-bit at position 10 on $auto$ff.cc:266:slice$1442 ($dffe) from module top. Setting constant 0-bit at position 11 on $auto$ff.cc:266:slice$1442 ($dffe) from module top. Setting constant 0-bit at position 12 on $auto$ff.cc:266:slice$1442 ($dffe) from module top. Setting constant 0-bit at position 13 on $auto$ff.cc:266:slice$1442 ($dffe) from module top. Setting constant 0-bit at position 14 on $auto$ff.cc:266:slice$1442 ($dffe) from module top. Setting constant 0-bit at position 15 on $auto$ff.cc:266:slice$1442 ($dffe) from module top. Setting constant 0-bit at position 16 on $auto$ff.cc:266:slice$1442 ($dffe) from module top. Setting constant 0-bit at position 17 on $auto$ff.cc:266:slice$1442 ($dffe) from module top. Setting constant 0-bit at position 18 on $auto$ff.cc:266:slice$1442 ($dffe) from module top. Setting constant 0-bit at position 19 on $auto$ff.cc:266:slice$1442 ($dffe) from module top. Setting constant 0-bit at position 20 on $auto$ff.cc:266:slice$1442 ($dffe) from module top. Setting constant 0-bit at position 21 on $auto$ff.cc:266:slice$1442 ($dffe) from module top. Setting constant 0-bit at position 22 on $auto$ff.cc:266:slice$1442 ($dffe) from module top. Setting constant 0-bit at position 23 on $auto$ff.cc:266:slice$1442 ($dffe) from module top. Setting constant 0-bit at position 24 on $auto$ff.cc:266:slice$1442 ($dffe) from module top. Setting constant 0-bit at position 25 on $auto$ff.cc:266:slice$1442 ($dffe) from module top. Setting constant 0-bit at position 26 on $auto$ff.cc:266:slice$1442 ($dffe) from module top. Setting constant 0-bit at position 27 on $auto$ff.cc:266:slice$1442 ($dffe) from module top. Setting constant 0-bit at position 28 on $auto$ff.cc:266:slice$1442 ($dffe) from module top. Setting constant 0-bit at position 29 on $auto$ff.cc:266:slice$1442 ($dffe) from module top. Setting constant 0-bit at position 0 on $auto$ff.cc:266:slice$1431 ($dffe) from module top. Setting constant 0-bit at position 1 on $auto$ff.cc:266:slice$1431 ($dffe) from module top. Setting constant 0-bit at position 2 on $auto$ff.cc:266:slice$1431 ($dffe) from module top. Setting constant 0-bit at position 3 on $auto$ff.cc:266:slice$1431 ($dffe) from module top. Setting constant 0-bit at position 4 on $auto$ff.cc:266:slice$1431 ($dffe) from module top. Setting constant 0-bit at position 5 on $auto$ff.cc:266:slice$1431 ($dffe) from module top. Setting constant 0-bit at position 6 on $auto$ff.cc:266:slice$1431 ($dffe) from module top. Setting constant 0-bit at position 7 on $auto$ff.cc:266:slice$1431 ($dffe) from module top. Setting constant 0-bit at position 8 on $auto$ff.cc:266:slice$1431 ($dffe) from module top. Setting constant 0-bit at position 9 on $auto$ff.cc:266:slice$1431 ($dffe) from module top. Setting constant 0-bit at position 10 on $auto$ff.cc:266:slice$1431 ($dffe) from module top. Setting constant 0-bit at position 11 on $auto$ff.cc:266:slice$1431 ($dffe) from module top. Setting constant 0-bit at position 12 on $auto$ff.cc:266:slice$1431 ($dffe) from module top. Setting constant 0-bit at position 13 on $auto$ff.cc:266:slice$1431 ($dffe) from module top. Setting constant 0-bit at position 14 on $auto$ff.cc:266:slice$1431 ($dffe) from module top. Setting constant 0-bit at position 15 on $auto$ff.cc:266:slice$1431 ($dffe) from module top. Setting constant 0-bit at position 16 on $auto$ff.cc:266:slice$1431 ($dffe) from module top. Setting constant 0-bit at position 17 on $auto$ff.cc:266:slice$1431 ($dffe) from module top. Setting constant 0-bit at position 18 on $auto$ff.cc:266:slice$1431 ($dffe) from module top. Setting constant 0-bit at position 19 on $auto$ff.cc:266:slice$1431 ($dffe) from module top. Setting constant 0-bit at position 20 on $auto$ff.cc:266:slice$1431 ($dffe) from module top. Setting constant 0-bit at position 21 on $auto$ff.cc:266:slice$1431 ($dffe) from module top. Setting constant 0-bit at position 22 on $auto$ff.cc:266:slice$1431 ($dffe) from module top. Setting constant 0-bit at position 23 on $auto$ff.cc:266:slice$1431 ($dffe) from module top. Setting constant 0-bit at position 24 on $auto$ff.cc:266:slice$1431 ($dffe) from module top. Setting constant 0-bit at position 25 on $auto$ff.cc:266:slice$1431 ($dffe) from module top. Setting constant 0-bit at position 26 on $auto$ff.cc:266:slice$1431 ($dffe) from module top. Setting constant 0-bit at position 27 on $auto$ff.cc:266:slice$1431 ($dffe) from module top. Setting constant 0-bit at position 28 on $auto$ff.cc:266:slice$1431 ($dffe) from module top. Setting constant 0-bit at position 29 on $auto$ff.cc:266:slice$1431 ($dffe) from module top. Setting constant 0-bit at position 30 on $auto$ff.cc:266:slice$1431 ($dffe) from module top. Setting constant 0-bit at position 2 on $auto$ff.cc:266:slice$1348 ($sdffe) from module top. Setting constant 0-bit at position 3 on $auto$ff.cc:266:slice$1348 ($sdffe) from module top. Setting constant 0-bit at position 4 on $auto$ff.cc:266:slice$1348 ($sdffe) from module top. Setting constant 0-bit at position 5 on $auto$ff.cc:266:slice$1348 ($sdffe) from module top. Setting constant 0-bit at position 6 on $auto$ff.cc:266:slice$1348 ($sdffe) from module top. Setting constant 0-bit at position 7 on $auto$ff.cc:266:slice$1348 ($sdffe) from module top. Setting constant 0-bit at position 1 on $auto$ff.cc:266:slice$1267 ($sdffe) from module top. Setting constant 0-bit at position 2 on $auto$ff.cc:266:slice$1267 ($sdffe) from module top. Setting constant 0-bit at position 3 on $auto$ff.cc:266:slice$1267 ($sdffe) from module top. Setting constant 0-bit at position 4 on $auto$ff.cc:266:slice$1267 ($sdffe) from module top. Setting constant 0-bit at position 5 on $auto$ff.cc:266:slice$1267 ($sdffe) from module top. Setting constant 0-bit at position 6 on $auto$ff.cc:266:slice$1267 ($sdffe) from module top. Setting constant 0-bit at position 7 on $auto$ff.cc:266:slice$1267 ($sdffe) from module top. Setting constant 0-bit at position 8 on $auto$ff.cc:266:slice$1267 ($sdffe) from module top. Setting constant 0-bit at position 9 on $auto$ff.cc:266:slice$1267 ($sdffe) from module top. Setting constant 0-bit at position 10 on $auto$ff.cc:266:slice$1267 ($sdffe) from module top. Setting constant 0-bit at position 11 on $auto$ff.cc:266:slice$1267 ($sdffe) from module top. Setting constant 0-bit at position 12 on $auto$ff.cc:266:slice$1267 ($sdffe) from module top. Setting constant 0-bit at position 13 on $auto$ff.cc:266:slice$1267 ($sdffe) from module top. Setting constant 0-bit at position 14 on $auto$ff.cc:266:slice$1267 ($sdffe) from module top. Setting constant 0-bit at position 15 on $auto$ff.cc:266:slice$1267 ($sdffe) from module top. Setting constant 0-bit at position 16 on $auto$ff.cc:266:slice$1267 ($sdffe) from module top. Setting constant 0-bit at position 17 on $auto$ff.cc:266:slice$1267 ($sdffe) from module top. Setting constant 0-bit at position 18 on $auto$ff.cc:266:slice$1267 ($sdffe) from module top. Setting constant 0-bit at position 19 on $auto$ff.cc:266:slice$1267 ($sdffe) from module top. Setting constant 0-bit at position 20 on $auto$ff.cc:266:slice$1267 ($sdffe) from module top. Setting constant 0-bit at position 21 on $auto$ff.cc:266:slice$1267 ($sdffe) from module top. Setting constant 0-bit at position 22 on $auto$ff.cc:266:slice$1267 ($sdffe) from module top. Setting constant 0-bit at position 23 on $auto$ff.cc:266:slice$1267 ($sdffe) from module top. Setting constant 0-bit at position 24 on $auto$ff.cc:266:slice$1267 ($sdffe) from module top. Setting constant 0-bit at position 25 on $auto$ff.cc:266:slice$1267 ($sdffe) from module top. Setting constant 0-bit at position 26 on $auto$ff.cc:266:slice$1267 ($sdffe) from module top. Setting constant 0-bit at position 27 on $auto$ff.cc:266:slice$1267 ($sdffe) from module top. Setting constant 0-bit at position 28 on $auto$ff.cc:266:slice$1267 ($sdffe) from module top. Setting constant 0-bit at position 29 on $auto$ff.cc:266:slice$1267 ($sdffe) from module top. Setting constant 0-bit at position 30 on $auto$ff.cc:266:slice$1267 ($sdffe) from module top. Setting constant 0-bit at position 31 on $auto$ff.cc:266:slice$1267 ($sdffe) from module top. 2.12.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 105 unused cells and 84 unused wires. 2.12.8. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 2.12.9. Rerunning OPT passes. (Maybe there is more to do..) 2.12.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 2.12.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 2.12.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 28 cells. 2.12.13. Executing OPT_DFF pass (perform DFF optimizations). 2.12.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 0 unused cells and 28 unused wires. 2.12.15. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 2.12.16. Rerunning OPT passes. (Maybe there is more to do..) 2.12.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 2.12.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 2.12.19. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 2.12.20. Executing OPT_DFF pass (perform DFF optimizations). 2.12.21. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 2.12.22. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 2.12.23. Finished OPT passes. (There is nothing left to do.) 2.13. Executing WREDUCE pass (reducing word size of cells). Removed top 22 address bits (of 32) from memory init port top.$flatten\cpu.\decode.$auto$mem.cc:328:emit$384 ($flatten\cpu.\decode.$auto$proc_rom.cc:150:do_switch$382). Removed top 1 bits (of 2) from port B of cell top.$auto$opt_dff.cc:195:make_patterns_logic$1472 ($ne). Removed top 2 bits (of 4) from port B of cell top.$auto$opt_dff.cc:195:make_patterns_logic$1479 ($ne). Removed top 2 bits (of 3) from port B of cell top.$auto$opt_dff.cc:195:make_patterns_logic$1492 ($ne). Removed top 1 bits (of 5) from port B of cell top.$auto$opt_dff.cc:195:make_patterns_logic$1359 ($ne). Removed top 1 bits (of 4) from port B of cell top.$auto$opt_dff.cc:195:make_patterns_logic$1361 ($ne). Removed top 1 bits (of 3) from port B of cell top.$auto$opt_dff.cc:195:make_patterns_logic$1363 ($ne). Removed top 2 bits (of 3) from port B of cell top.$auto$opt_dff.cc:195:make_patterns_logic$1365 ($ne). Removed top 3 bits (of 4) from port B of cell top.$auto$opt_dff.cc:195:make_patterns_logic$1466 ($ne). Removed top 1 bits (of 3) from port B of cell top.$auto$opt_dff.cc:195:make_patterns_logic$1468 ($ne). Removed top 2 bits (of 4) from port B of cell top.$auto$opt_dff.cc:195:make_patterns_logic$1300 ($ne). Removed top 2 bits (of 3) from port B of cell top.$auto$opt_dff.cc:195:make_patterns_logic$1282 ($ne). Removed top 1 bits (of 3) from port B of cell top.$flatten\cpu.\exception_router.$4 ($eq). Removed top 1 bits (of 3) from port B of cell top.$flatten\cpu.\exception_router.$58 ($eq). Removed top 3 bits (of 5) from port B of cell top.$flatten\cpu.\decode.$procmux$864_CMP0 ($eq). Removed top 1 bits (of 5) from port B of cell top.$flatten\cpu.\decode.$procmux$865_CMP0 ($eq). Removed top 1 bits (of 5) from port B of cell top.$flatten\cpu.\decode.$procmux$872_CMP0 ($eq). Removed top 2 bits (of 5) from port B of cell top.$flatten\cpu.\decode.$procmux$873_CMP0 ($eq). Removed top 1 bits (of 5) from port B of cell top.$flatten\cpu.\decode.$procmux$874_CMP0 ($eq). Removed top 4 bits (of 8) from mux cell top.$flatten\cpu.\decode.$procmux$876 ($mux). Removed top 2 bits (of 5) from port B of cell top.$flatten\cpu.\decode.$procmux$878_CMP0 ($eq). Removed top 30 bits (of 31) from mux cell top.$flatten\cpu.\decode.$procmux$1017 ($mux). Removed top 27 bits (of 31) from mux cell top.$flatten\cpu.\decode.$procmux$1019 ($mux). Removed top 27 bits (of 31) from mux cell top.$flatten\cpu.\decode.$procmux$1021 ($mux). Removed top 27 bits (of 31) from mux cell top.$flatten\cpu.\decode.$procmux$1023 ($mux). Removed top 27 bits (of 31) from mux cell top.$flatten\cpu.\decode.$procmux$1025 ($mux). Removed top 29 bits (of 31) from mux cell top.$flatten\cpu.\decode.$procmux$1027 ($mux). Removed top 1 bits (of 2) from port B of cell top.$flatten\cpu.\datapath.\pc_mod.$procmux$1180_CMP0 ($eq). Removed top 30 bits (of 32) from mux cell top.$flatten\cpu.\datapath.\regfile.$procmux$1172 ($mux). Removed top 1 bits (of 2) from port B of cell top.$flatten\cpu.\datapath.\csrfile.$32 ($eq). Removed top 1 bits (of 9) from port Y of cell top.$flatten\cpu.\control.\sequencer.$3 ($add). Removed top 1 bits (of 2) from port B of cell top.$flatten\cpu.\control.$procmux$1189_CMP0 ($eq). Removed top 1 bits (of 2) from port B of cell top.$flatten\cpu.\control.\sequencer.$procmux$1203_CMP0 ($eq). Removed top 1 bits (of 33) from port A of cell top.$flatten\cpu.\alu.\sub.$3 ($sub). Removed top 1 bits (of 33) from port B of cell top.$flatten\cpu.\alu.\sub.$3 ($sub). Removed top 1 bits (of 34) from port Y of cell top.$flatten\cpu.\alu.\sub.$3 ($sub). Removed top 3 bits (of 4) from port B of cell top.$flatten\cpu.\alu.$procmux$1227_CMP0 ($eq). Removed top 2 bits (of 4) from port B of cell top.$flatten\cpu.\alu.$procmux$1226_CMP0 ($eq). Removed top 1 bits (of 2) from port B of cell top.$flatten\cpu.\alu.$18 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\cpu.\alu.$procmux$1221_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\cpu.\alu.$procmux$1222_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\cpu.\alu.$procmux$1223_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\cpu.\alu.$procmux$1224_CMP0 ($eq). Removed top 2 bits (of 4) from port B of cell top.$flatten\cpu.\alu.$procmux$1225_CMP0 ($eq). Removed top 1 bits (of 3) from port B of cell top.$flatten\cpu.$procmux$782_CMP0 ($eq). Removed top 1 bits (of 3) from port B of cell top.$flatten\cpu.$procmux$781_CMP0 ($eq). Removed top 1 bits (of 3) from port B of cell top.$flatten\cpu.$procmux$771_CMP0 ($eq). Removed top 1 bits (of 3) from port B of cell top.$flatten\cpu.$procmux$770_CMP0 ($eq). Removed top 2 bits (of 3) from port B of cell top.$flatten\cpu.$procmux$769_CMP0 ($eq). Removed top 24 bits (of 32) from mux cell top.$flatten\cpu.$procmux$743 ($mux). Removed top 16 bits (of 32) from mux cell top.$flatten\cpu.$procmux$740 ($mux). Removed top 16 bits (of 32) from mux cell top.$flatten\cpu.$procmux$738 ($mux). Removed top 1 bits (of 2) from port B of cell top.$flatten\cpu.$procmux$653_CMP0 ($eq). Removed top 1 bits (of 6) from mux cell top.$flatten\cpu.$procmux$637 ($mux). Removed top 1 bits (of 6) from mux cell top.$flatten\cpu.$procmux$634 ($pmux). Removed top 1 bits (of 6) from mux cell top.$flatten\cpu.$procmux$631 ($pmux). Removed top 2 bits (of 3) from port B of cell top.$flatten\cpu.$procmux$783_CMP0 ($eq). Removed top 2 bits (of 3) from port B of cell top.$flatten\cpu.\exception_router.$2 ($eq). Removed top 1 bits (of 31) from port Y of cell top.$flatten\cpu.\datapath.\pc_mod.$3 ($add). Removed top 1 bits (of 33) from port Y of cell top.$flatten\cpu.\alu.\add.$3 ($add). Removed top 1 bits (of 2) from port B of cell top.$auto$opt_dff.cc:195:make_patterns_logic$1503 ($ne). Removed top 3 bits (of 8) from FF cell top.$auto$ff.cc:266:slice$1350 ($sdffe). Removed top 5 bits (of 30) from port B of cell top.$flatten\decoder.$procmux$598_CMP0 ($eq). Removed top 6 bits (of 30) from port B of cell top.$flatten\decoder.$procmux$596_CMP0 ($eq). Removed top 5 bits (of 30) from port B of cell top.$flatten\decoder.$procmux$594_CMP0 ($eq). Removed top 1 bits (of 16) from port Y of cell top.$flatten\timer.$3 ($add). Removed top 3 bits (of 4) from port B of cell top.$auto$opt_dff.cc:195:make_patterns_logic$1513 ($ne). Removed top 1 bits (of 5) from port Y of cell top.$flatten\serial.\ser_internal.$13 ($sub). Removed top 1 bits (of 12) from port Y of cell top.$flatten\serial.\ser_internal.$20 ($sub). Removed top 1 bits (of 5) from port Y of cell top.$flatten\serial.\ser_internal.$61 ($sub). Removed top 1 bits (of 12) from port Y of cell top.$flatten\serial.\ser_internal.$74 ($sub). Removed top 1 bits (of 9) from port Y of cell top.$flatten\cd_sync.$7 ($add). Removed top 2 bits (of 4) from mux cell top.$flatten\cpu.\decode.$procmux$1025 ($mux). Removed top 16 bits (of 32) from mux cell top.$flatten\cpu.$procmux$747 ($mux). Removed top 2 bits (of 4) from mux cell top.$flatten\cpu.\decode.$procmux$1023 ($mux). Removed top 24 bits (of 32) from mux cell top.$flatten\cpu.$procmux$745 ($mux). Removed top 2 bits (of 4) from mux cell top.$flatten\cpu.\decode.$procmux$1021 ($mux). Removed top 1 bits (of 9) from wire top.$flatten\cd_sync.$5. Removed top 1 bits (of 6) from wire top.$flatten\cpu.$procmux$637_Y. Removed top 16 bits (of 32) from wire top.$flatten\cpu.$procmux$738_Y. Removed top 31 bits (of 32) from wire top.$flatten\cpu.$procmux$743_Y. Removed top 24 bits (of 32) from wire top.$flatten\cpu.$procmux$745_Y. Removed top 19 bits (of 32) from wire top.$flatten\cpu.$procmux$747_Y. Removed top 4 bits (of 32) from wire top.$flatten\cpu.$procmux$754_Y. Removed top 1 bits (of 9) from wire top.$flatten\cpu.\control.\sequencer.$1. Removed top 1 bits (of 31) from wire top.$flatten\cpu.\datapath.\pc_mod.$1. Removed top 4 bits (of 30) from wire top.$flatten\cpu.\datapath.\pc_mod.$procmux$1178_Y. Removed top 30 bits (of 31) from wire top.$flatten\cpu.\decode.$procmux$1017_Y. Removed top 30 bits (of 31) from wire top.$flatten\cpu.\decode.$procmux$1019_Y. Removed top 4 bits (of 8) from wire top.$flatten\cpu.\decode.$procmux$876_Y. Removed top 1 bits (of 5) from wire top.$flatten\serial.\ser_internal.$11. Removed top 1 bits (of 12) from wire top.$flatten\serial.\ser_internal.$18. Removed top 1 bits (of 5) from wire top.$flatten\serial.\ser_internal.$59. Removed top 1 bits (of 12) from wire top.$flatten\serial.\ser_internal.$72. Removed top 1 bits (of 16) from wire top.$flatten\timer.$1. Removed top 6 bits (of 8) from wire top.decoder_led__dat_r. Removed top 31 bits (of 32) from wire top.decoder_timer__dat_r. Removed top 6 bits (of 8) from wire top.leds_bus__dat_r. Removed top 6 bits (of 8) from wire top.leds_inp. Removed top 3 bits (of 8) from wire top.leds_leds. Removed top 31 bits (of 32) from wire top.timer_bus__dat_r. 2.14. Executing PEEPOPT pass (run peephole optimizers). 2.15. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 0 unused cells and 26 unused wires. 2.16. Executing SHARE pass (SAT-based resource sharing). 2.17. Executing TECHMAP pass (map to technology primitives). 2.17.1. Executing Verilog-2005 frontend: /home/william/.local/bin/../share/yosys/cmp2lut.v Parsing Verilog input from `/home/william/.local/bin/../share/yosys/cmp2lut.v' to AST representation. Generating RTLIL representation for module `\_90_lut_cmp_'. Successfully finished Verilog frontend. 2.17.2. Continuing TECHMAP pass. Using template $paramod$c007e08929458199fba5a42550659350d0289be2\_90_lut_cmp_ for cells of type $ge. No more expansions possible. 2.18. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 2.19. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 0 unused cells and 3 unused wires. 2.20. Executing ALUMACC pass (create $alu and $macc cells). Extracting $alu and $macc cells in module top: creating $macc model for $flatten\cd_sync.$7 ($add). creating $macc model for $flatten\cpu.\alu.\add.$3 ($add). creating $macc model for $flatten\cpu.\alu.\sub.$3 ($sub). creating $macc model for $flatten\cpu.\control.\sequencer.$3 ($add). creating $macc model for $flatten\cpu.\datapath.\pc_mod.$3 ($add). creating $macc model for $flatten\serial.\ser_internal.$13 ($sub). creating $macc model for $flatten\serial.\ser_internal.$20 ($sub). creating $macc model for $flatten\serial.\ser_internal.$61 ($sub). creating $macc model for $flatten\serial.\ser_internal.$74 ($sub). creating $macc model for $flatten\timer.$3 ($add). creating $alu model for $macc $flatten\timer.$3. creating $alu model for $macc $flatten\serial.\ser_internal.$74. creating $alu model for $macc $flatten\serial.\ser_internal.$61. creating $alu model for $macc $flatten\serial.\ser_internal.$20. creating $alu model for $macc $flatten\serial.\ser_internal.$13. creating $alu model for $macc $flatten\cpu.\datapath.\pc_mod.$3. creating $alu model for $macc $flatten\cpu.\control.\sequencer.$3. creating $alu model for $macc $flatten\cpu.\alu.\sub.$3. creating $alu model for $macc $flatten\cpu.\alu.\add.$3. creating $alu model for $macc $flatten\cd_sync.$7. creating $alu cell for $flatten\cd_sync.$7: $auto$alumacc.cc:485:replace_alu$1554 creating $alu cell for $flatten\cpu.\alu.\add.$3: $auto$alumacc.cc:485:replace_alu$1557 creating $alu cell for $flatten\cpu.\alu.\sub.$3: $auto$alumacc.cc:485:replace_alu$1560 creating $alu cell for $flatten\cpu.\control.\sequencer.$3: $auto$alumacc.cc:485:replace_alu$1563 creating $alu cell for $flatten\cpu.\datapath.\pc_mod.$3: $auto$alumacc.cc:485:replace_alu$1566 creating $alu cell for $flatten\serial.\ser_internal.$13: $auto$alumacc.cc:485:replace_alu$1569 creating $alu cell for $flatten\serial.\ser_internal.$20: $auto$alumacc.cc:485:replace_alu$1572 creating $alu cell for $flatten\serial.\ser_internal.$61: $auto$alumacc.cc:485:replace_alu$1575 creating $alu cell for $flatten\serial.\ser_internal.$74: $auto$alumacc.cc:485:replace_alu$1578 creating $alu cell for $flatten\timer.$3: $auto$alumacc.cc:485:replace_alu$1581 created 10 $alu and 0 $macc cells. 2.21. Executing OPT pass (performing simple optimizations). 2.21.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 2.21.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 2.21.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 2.21.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 2.21.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 2.21.6. Executing OPT_DFF pass (perform DFF optimizations). Setting constant 0-bit at position 0 on $auto$ff.cc:266:slice$1391 ($sdff) from module top. Setting constant 0-bit at position 1 on $auto$ff.cc:266:slice$1391 ($sdff) from module top. Setting constant 0-bit at position 2 on $auto$ff.cc:266:slice$1391 ($sdff) from module top. Setting constant 0-bit at position 3 on $auto$ff.cc:266:slice$1391 ($sdff) from module top. Setting constant 0-bit at position 4 on $auto$ff.cc:266:slice$1391 ($sdff) from module top. Setting constant 0-bit at position 5 on $auto$ff.cc:266:slice$1391 ($sdff) from module top. Setting constant 0-bit at position 6 on $auto$ff.cc:266:slice$1391 ($sdff) from module top. Setting constant 0-bit at position 7 on $auto$ff.cc:266:slice$1391 ($sdff) from module top. Setting constant 0-bit at position 8 on $auto$ff.cc:266:slice$1391 ($sdff) from module top. Setting constant 0-bit at position 9 on $auto$ff.cc:266:slice$1391 ($sdff) from module top. Setting constant 0-bit at position 10 on $auto$ff.cc:266:slice$1391 ($sdff) from module top. Setting constant 0-bit at position 11 on $auto$ff.cc:266:slice$1391 ($sdff) from module top. Setting constant 0-bit at position 12 on $auto$ff.cc:266:slice$1391 ($sdff) from module top. Setting constant 0-bit at position 13 on $auto$ff.cc:266:slice$1391 ($sdff) from module top. Setting constant 0-bit at position 14 on $auto$ff.cc:266:slice$1391 ($sdff) from module top. Setting constant 0-bit at position 15 on $auto$ff.cc:266:slice$1391 ($sdff) from module top. Setting constant 0-bit at position 16 on $auto$ff.cc:266:slice$1391 ($sdff) from module top. Setting constant 0-bit at position 17 on $auto$ff.cc:266:slice$1391 ($sdff) from module top. Setting constant 0-bit at position 18 on $auto$ff.cc:266:slice$1391 ($sdff) from module top. Setting constant 0-bit at position 19 on $auto$ff.cc:266:slice$1391 ($sdff) from module top. Setting constant 0-bit at position 20 on $auto$ff.cc:266:slice$1391 ($sdff) from module top. Setting constant 0-bit at position 21 on $auto$ff.cc:266:slice$1391 ($sdff) from module top. Setting constant 0-bit at position 22 on $auto$ff.cc:266:slice$1391 ($sdff) from module top. Setting constant 0-bit at position 23 on $auto$ff.cc:266:slice$1391 ($sdff) from module top. Setting constant 0-bit at position 24 on $auto$ff.cc:266:slice$1391 ($sdff) from module top. Setting constant 0-bit at position 25 on $auto$ff.cc:266:slice$1391 ($sdff) from module top. Setting constant 0-bit at position 26 on $auto$ff.cc:266:slice$1391 ($sdff) from module top. Setting constant 0-bit at position 27 on $auto$ff.cc:266:slice$1391 ($sdff) from module top. 2.21.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 1 unused cells and 1 unused wires. 2.21.8. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 2.21.9. Rerunning OPT passes. (Maybe there is more to do..) 2.21.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 2.21.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 2.21.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 2.21.13. Executing OPT_DFF pass (perform DFF optimizations). 2.21.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 2.21.15. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 2.21.16. Finished OPT passes. (There is nothing left to do.) 2.22. Executing MEMORY pass. 2.22.1. Executing OPT_MEM pass (optimize memories). Performed a total of 0 transformations. 2.22.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations). Performed a total of 0 transformations. 2.22.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths). 2.22.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs). 2.22.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd). Checking read port `$flatten\cpu.\decode.$auto$proc_rom.cc:150:do_switch$382'[0] in module `\top': merging output FF to cell. 2.22.6. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 1 unused cells and 3 unused wires. 2.22.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). 2.22.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide). Performed a total of 0 transformations. 2.22.9. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 2.22.10. Executing MEMORY_COLLECT pass (generating $mem cells). 2.23. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 2.24. Executing MEMORY_LIBMAP pass (mapping memories to cells). mapping memory top.$flatten\cpu.\decode.$auto$proc_rom.cc:150:do_switch$382 via $__ICE40_RAM4K_ mapping memory top.cpu.control.ucoderom.rdport via $__ICE40_RAM4K_ mapping memory top.cpu.datapath.regfile.rdport$1 via $__ICE40_RAM4K_ mapping memory top.mem.rdport$2 via $__ICE40_RAM4K_ 2.25. Executing TECHMAP pass (map to technology primitives). 2.25.1. Executing Verilog-2005 frontend: /home/william/.local/bin/../share/yosys/ice40/brams_map.v Parsing Verilog input from `/home/william/.local/bin/../share/yosys/ice40/brams_map.v' to AST representation. Generating RTLIL representation for module `\$__ICE40_RAM4K_'. Successfully finished Verilog frontend. 2.25.2. Executing Verilog-2005 frontend: /home/william/.local/bin/../share/yosys/ice40/spram_map.v Parsing Verilog input from `/home/william/.local/bin/../share/yosys/ice40/spram_map.v' to AST representation. Generating RTLIL representation for module `\$__ICE40_SPRAM_'. Successfully finished Verilog frontend. 2.25.3. Continuing TECHMAP pass. Using template $paramod$00f7e8a2952599cb948f65026692096ef3318065\$__ICE40_RAM4K_ for cells of type $__ICE40_RAM4K_. Using template $paramod$e56689e2fe4b5e6e25cbbfccd1205e28c9c679b7\$__ICE40_RAM4K_ for cells of type $__ICE40_RAM4K_. Using template $paramod$221ad0ab8d29acb46e9d882d87f518da8b1cc318\$__ICE40_RAM4K_ for cells of type $__ICE40_RAM4K_. Using template $paramod$d6f9364cea7172a3f49a07bf07e0907eb809b8ff\$__ICE40_RAM4K_ for cells of type $__ICE40_RAM4K_. Using template $paramod$83ff91327c3fec7a7628263a288a01105e867a29\$__ICE40_RAM4K_ for cells of type $__ICE40_RAM4K_. Using template $paramod$47b1ee1be09612a124f5ebcfd24f175333617f2b\$__ICE40_RAM4K_ for cells of type $__ICE40_RAM4K_. Using template $paramod$2d83a12dadf386f3a7e0f421392cbddbe49d4b7b\$__ICE40_RAM4K_ for cells of type $__ICE40_RAM4K_. Using template $paramod$ce6753f9ba1351fb764f366f9662efc706105d4d\$__ICE40_RAM4K_ for cells of type $__ICE40_RAM4K_. Using template $paramod$f4463f47038605be80cf26acd93c6cb1ab1054c1\$__ICE40_RAM4K_ for cells of type $__ICE40_RAM4K_. Using template $paramod$ac69fbd6afee454f50ea8b4d75d2ffceda8958ec\$__ICE40_RAM4K_ for cells of type $__ICE40_RAM4K_. Using template $paramod$ad461e9a6f0c9639c07210014d8a7ccbf79cd51b\$__ICE40_RAM4K_ for cells of type $__ICE40_RAM4K_. Using template $paramod$6cb46ff6a59d58eb422e7391f5d3b8cb5b264c8c\$__ICE40_RAM4K_ for cells of type $__ICE40_RAM4K_. Using template $paramod$253ff478367301d0bd9f650a148e81bdd03cbb2e\$__ICE40_RAM4K_ for cells of type $__ICE40_RAM4K_. Using template $paramod$3a35a32f7a66d5378694f0e173cf4a7bf81c2202\$__ICE40_RAM4K_ for cells of type $__ICE40_RAM4K_. No more expansions possible. 2.26. Executing ICE40_BRAMINIT pass. 2.27. Executing OPT pass (performing simple optimizations). 2.27.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 2.27.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 1 cells. 2.27.3. Executing OPT_DFF pass (perform DFF optimizations). 2.27.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 6 unused cells and 277 unused wires. 2.27.5. Finished fast OPT passes. 2.28. Executing MEMORY_MAP pass (converting memories to logic and flip-flops). 2.29. Executing OPT pass (performing simple optimizations). 2.29.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 2.29.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 2.29.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 2.29.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Consolidated identical input bits for $mux cell $flatten\cpu.$procmux$626: Old ports: A={ 1'0 \cpu.decode.csr_encoding }, B={ 1'0 \cpu.control.ucoderom.ucode_mem_r_data [3:0] }, Y=\cpu.datapath.csrfile.pub__adr New ports: A=\cpu.decode.csr_encoding, B=\cpu.control.ucoderom.ucode_mem_r_data [3:0], Y=\cpu.datapath.csrfile.pub__adr [3:0] New connections: \cpu.datapath.csrfile.pub__adr [4] = 1'0 Consolidated identical input bits for $mux cell $flatten\cpu.$procmux$643: Old ports: A=4'0011, B=4'1100, Y=$flatten\cpu.$procmux$643_Y New ports: A=2'01, B=2'10, Y={ $flatten\cpu.$procmux$643_Y [2] $flatten\cpu.$procmux$643_Y [0] } New connections: { $flatten\cpu.$procmux$643_Y [3] $flatten\cpu.$procmux$643_Y [1] } = { $flatten\cpu.$procmux$643_Y [2] $flatten\cpu.$procmux$643_Y [0] } Consolidated identical input bits for $mux cell $flatten\cpu.$procmux$647: Old ports: A=4'1000, B=4'0100, Y=$flatten\cpu.$procmux$647_Y New ports: A=2'10, B=2'01, Y=$flatten\cpu.$procmux$647_Y [3:2] New connections: $flatten\cpu.$procmux$647_Y [1:0] = 2'00 New ctrl vector for $pmux cell $flatten\cpu.$procmux$686: $flatten\cpu.$procmux$641_CMP New ctrl vector for $pmux cell $flatten\cpu.$procmux$704: $auto$opt_reduce.cc:134:opt_pmux$1941 Consolidated identical input bits for $pmux cell $flatten\cpu.$procmux$721: Old ports: A=\cpu.alu.data__o [7:0], B={ \cpu.alu.data__o [7:0] \cpu.alu.data__o [7:0] }, Y=$flatten\cpu.$procmux$721_Y New connections: $flatten\cpu.$procmux$721_Y = \cpu.alu.data__o [7:0] Consolidated identical input bits for $mux cell $flatten\cpu.$procmux$747: Old ports: A={ 8'00000000 $auto$wreduce.cc:461:run$1531 [7:0] }, B={ 8'00000000 \cpu.bus__dat_r [7:0] }, Y=$auto$wreduce.cc:461:run$1532 [15:0] New ports: A=$auto$wreduce.cc:461:run$1531 [7:0], B=\cpu.bus__dat_r [7:0], Y=$auto$wreduce.cc:461:run$1532 [7:0] New connections: $auto$wreduce.cc:461:run$1532 [15:8] = 8'00000000 Consolidated identical input bits for $mux cell $flatten\cpu.$procmux$761: Old ports: A={ 16'0000000000000000 \cpu.raw_dat_r [15:0] }, B={ \cpu.raw_dat_r [15] \cpu.raw_dat_r [15] \cpu.raw_dat_r [15] \cpu.raw_dat_r [15] \cpu.raw_dat_r [15] \cpu.raw_dat_r [15] \cpu.raw_dat_r [15] \cpu.raw_dat_r [15] \cpu.raw_dat_r [15] \cpu.raw_dat_r [15] \cpu.raw_dat_r [15] \cpu.raw_dat_r [15] \cpu.raw_dat_r [15] \cpu.raw_dat_r [15] \cpu.raw_dat_r [15] \cpu.raw_dat_r [15] \cpu.raw_dat_r [15:0] }, Y=$flatten\cpu.$procmux$761_Y New ports: A=1'0, B=\cpu.raw_dat_r [15], Y=$flatten\cpu.$procmux$761_Y [16] New connections: { $flatten\cpu.$procmux$761_Y [31:17] $flatten\cpu.$procmux$761_Y [15:0] } = { $flatten\cpu.$procmux$761_Y [16] $flatten\cpu.$procmux$761_Y [16] $flatten\cpu.$procmux$761_Y [16] $flatten\cpu.$procmux$761_Y [16] $flatten\cpu.$procmux$761_Y [16] $flatten\cpu.$procmux$761_Y [16] $flatten\cpu.$procmux$761_Y [16] $flatten\cpu.$procmux$761_Y [16] $flatten\cpu.$procmux$761_Y [16] $flatten\cpu.$procmux$761_Y [16] $flatten\cpu.$procmux$761_Y [16] $flatten\cpu.$procmux$761_Y [16] $flatten\cpu.$procmux$761_Y [16] $flatten\cpu.$procmux$761_Y [16] $flatten\cpu.$procmux$761_Y [16] \cpu.raw_dat_r [15:0] } Consolidated identical input bits for $mux cell $flatten\cpu.$procmux$765: Old ports: A={ 24'000000000000000000000000 \cpu.raw_dat_r [7:0] }, B={ \cpu.raw_dat_r [7] \cpu.raw_dat_r [7] \cpu.raw_dat_r [7] \cpu.raw_dat_r [7] \cpu.raw_dat_r [7] \cpu.raw_dat_r [7] \cpu.raw_dat_r [7] \cpu.raw_dat_r [7] \cpu.raw_dat_r [7] \cpu.raw_dat_r [7] \cpu.raw_dat_r [7] \cpu.raw_dat_r [7] \cpu.raw_dat_r [7] \cpu.raw_dat_r [7] \cpu.raw_dat_r [7] \cpu.raw_dat_r [7] \cpu.raw_dat_r [7] \cpu.raw_dat_r [7] \cpu.raw_dat_r [7] \cpu.raw_dat_r [7] \cpu.raw_dat_r [7] \cpu.raw_dat_r [7] \cpu.raw_dat_r [7] \cpu.raw_dat_r [7] \cpu.raw_dat_r [7:0] }, Y=$flatten\cpu.$procmux$765_Y New ports: A=1'0, B=\cpu.raw_dat_r [7], Y=$flatten\cpu.$procmux$765_Y [8] New connections: { $flatten\cpu.$procmux$765_Y [31:9] $flatten\cpu.$procmux$765_Y [7:0] } = { $flatten\cpu.$procmux$765_Y [8] $flatten\cpu.$procmux$765_Y [8] $flatten\cpu.$procmux$765_Y [8] $flatten\cpu.$procmux$765_Y [8] $flatten\cpu.$procmux$765_Y [8] $flatten\cpu.$procmux$765_Y [8] $flatten\cpu.$procmux$765_Y [8] $flatten\cpu.$procmux$765_Y [8] $flatten\cpu.$procmux$765_Y [8] $flatten\cpu.$procmux$765_Y [8] $flatten\cpu.$procmux$765_Y [8] $flatten\cpu.$procmux$765_Y [8] $flatten\cpu.$procmux$765_Y [8] $flatten\cpu.$procmux$765_Y [8] $flatten\cpu.$procmux$765_Y [8] $flatten\cpu.$procmux$765_Y [8] $flatten\cpu.$procmux$765_Y [8] $flatten\cpu.$procmux$765_Y [8] $flatten\cpu.$procmux$765_Y [8] $flatten\cpu.$procmux$765_Y [8] $flatten\cpu.$procmux$765_Y [8] $flatten\cpu.$procmux$765_Y [8] $flatten\cpu.$procmux$765_Y [8] \cpu.raw_dat_r [7:0] } Consolidated identical input bits for $mux cell $flatten\cpu.\decode.$procmux$1019: Old ports: A={ 3'001 $auto$wreduce.cc:461:run$1537 [0] }, B=4'1011, Y=$auto$wreduce.cc:461:run$1538 [3:0] New ports: A={ 1'0 $auto$wreduce.cc:461:run$1537 [0] }, B=2'11, Y={ $auto$wreduce.cc:461:run$1538 [3] $auto$wreduce.cc:461:run$1538 [0] } New connections: $auto$wreduce.cc:461:run$1538 [2:1] = 2'01 Consolidated identical input bits for $mux cell $flatten\cpu.\decode.$procmux$876: Old ports: A={ 1'0 \cpu.bus__dat_r [14:12] }, B={ \cpu.bus__dat_r [30] \cpu.bus__dat_r [14:12] }, Y=$auto$wreduce.cc:461:run$1539 [3:0] New ports: A=1'0, B=\cpu.bus__dat_r [30], Y=$auto$wreduce.cc:461:run$1539 [3] New connections: $auto$wreduce.cc:461:run$1539 [2:0] = \cpu.bus__dat_r [14:12] Consolidated identical input bits for $pmux cell $flatten\cpu.\decode.$procmux$916: Old ports: A={ \cpu.bus__dat_r [31:12] 12'000000000000 }, B={ \cpu.bus__dat_r [31] \cpu.bus__dat_r [31] \cpu.bus__dat_r [31] \cpu.bus__dat_r [31] \cpu.bus__dat_r [31] \cpu.bus__dat_r [31] \cpu.bus__dat_r [31] \cpu.bus__dat_r [31] \cpu.bus__dat_r [31] \cpu.bus__dat_r [31] \cpu.bus__dat_r [31] \cpu.bus__dat_r [31] \cpu.bus__dat_r [19:12] \cpu.bus__dat_r [20] \cpu.bus__dat_r [30:21] 1'0 \cpu.bus__dat_r [31] \cpu.bus__dat_r [31] \cpu.bus__dat_r [31] \cpu.bus__dat_r [31] \cpu.bus__dat_r [31] \cpu.bus__dat_r [31] \cpu.bus__dat_r [31] \cpu.bus__dat_r [31] \cpu.bus__dat_r [31] \cpu.bus__dat_r [31] \cpu.bus__dat_r [31] \cpu.bus__dat_r [31] \cpu.bus__dat_r [31] \cpu.bus__dat_r [31] \cpu.bus__dat_r [31] \cpu.bus__dat_r [31] \cpu.bus__dat_r [31] \cpu.bus__dat_r [31] \cpu.bus__dat_r [31] \cpu.bus__dat_r [31] \cpu.bus__dat_r [7] \cpu.bus__dat_r [30:25] \cpu.bus__dat_r [11:8] 1'0 \cpu.bus__dat_r [31] \cpu.bus__dat_r [31] \cpu.bus__dat_r [31] \cpu.bus__dat_r [31] \cpu.bus__dat_r [31] \cpu.bus__dat_r [31] \cpu.bus__dat_r [31] \cpu.bus__dat_r [31] \cpu.bus__dat_r [31] \cpu.bus__dat_r [31] \cpu.bus__dat_r [31] \cpu.bus__dat_r [31] \cpu.bus__dat_r [31] \cpu.bus__dat_r [31] \cpu.bus__dat_r [31] \cpu.bus__dat_r [31] \cpu.bus__dat_r [31] \cpu.bus__dat_r [31] \cpu.bus__dat_r [31] \cpu.bus__dat_r [31] \cpu.bus__dat_r [31:20] \cpu.bus__dat_r [31] \cpu.bus__dat_r [31] \cpu.bus__dat_r [31] \cpu.bus__dat_r [31] \cpu.bus__dat_r [31] \cpu.bus__dat_r [31] \cpu.bus__dat_r [31] \cpu.bus__dat_r [31] \cpu.bus__dat_r [31] \cpu.bus__dat_r [31] \cpu.bus__dat_r [31] \cpu.bus__dat_r [31] \cpu.bus__dat_r [31] \cpu.bus__dat_r [31] \cpu.bus__dat_r [31] \cpu.bus__dat_r [31] \cpu.bus__dat_r [31] \cpu.bus__dat_r [31] \cpu.bus__dat_r [31] \cpu.bus__dat_r [31] \cpu.bus__dat_r [31:25] \cpu.bus__dat_r [11:7] }, Y=$flatten\cpu.\decode.$procmux$916_Y New ports: A={ \cpu.bus__dat_r [30:12] 12'000000000000 }, B={ \cpu.bus__dat_r [31] \cpu.bus__dat_r [31] \cpu.bus__dat_r [31] \cpu.bus__dat_r [31] \cpu.bus__dat_r [31] \cpu.bus__dat_r [31] \cpu.bus__dat_r [31] \cpu.bus__dat_r [31] \cpu.bus__dat_r [31] \cpu.bus__dat_r [31] \cpu.bus__dat_r [31] \cpu.bus__dat_r [19:12] \cpu.bus__dat_r [20] \cpu.bus__dat_r [30:21] 1'0 \cpu.bus__dat_r [31] \cpu.bus__dat_r [31] \cpu.bus__dat_r [31] \cpu.bus__dat_r [31] \cpu.bus__dat_r [31] \cpu.bus__dat_r [31] \cpu.bus__dat_r [31] \cpu.bus__dat_r [31] \cpu.bus__dat_r [31] \cpu.bus__dat_r [31] \cpu.bus__dat_r [31] \cpu.bus__dat_r [31] \cpu.bus__dat_r [31] \cpu.bus__dat_r [31] \cpu.bus__dat_r [31] \cpu.bus__dat_r [31] \cpu.bus__dat_r [31] \cpu.bus__dat_r [31] \cpu.bus__dat_r [31] \cpu.bus__dat_r [7] \cpu.bus__dat_r [30:25] \cpu.bus__dat_r [11:8] 1'0 \cpu.bus__dat_r [31] \cpu.bus__dat_r [31] \cpu.bus__dat_r [31] \cpu.bus__dat_r [31] \cpu.bus__dat_r [31] \cpu.bus__dat_r [31] \cpu.bus__dat_r [31] \cpu.bus__dat_r [31] \cpu.bus__dat_r [31] \cpu.bus__dat_r [31] \cpu.bus__dat_r [31] \cpu.bus__dat_r [31] \cpu.bus__dat_r [31] \cpu.bus__dat_r [31] \cpu.bus__dat_r [31] \cpu.bus__dat_r [31] \cpu.bus__dat_r [31] \cpu.bus__dat_r [31] \cpu.bus__dat_r [31] \cpu.bus__dat_r [31:20] \cpu.bus__dat_r [31] \cpu.bus__dat_r [31] \cpu.bus__dat_r [31] \cpu.bus__dat_r [31] \cpu.bus__dat_r [31] \cpu.bus__dat_r [31] \cpu.bus__dat_r [31] \cpu.bus__dat_r [31] \cpu.bus__dat_r [31] \cpu.bus__dat_r [31] \cpu.bus__dat_r [31] \cpu.bus__dat_r [31] \cpu.bus__dat_r [31] \cpu.bus__dat_r [31] \cpu.bus__dat_r [31] \cpu.bus__dat_r [31] \cpu.bus__dat_r [31] \cpu.bus__dat_r [31] \cpu.bus__dat_r [31] \cpu.bus__dat_r [31:25] \cpu.bus__dat_r [11:7] }, Y=$flatten\cpu.\decode.$procmux$916_Y [30:0] New connections: $flatten\cpu.\decode.$procmux$916_Y [31] = \cpu.bus__dat_r [31] Consolidated identical input bits for $mux cell $flatten\cpu.\exception_router.$procmux$804: Old ports: A=31'0000000000000000000000000000000, B=31'0000000000000000000000000000100, Y=$flatten\cpu.\exception_router.$procmux$804_Y New ports: A=1'0, B=1'1, Y=$flatten\cpu.\exception_router.$procmux$804_Y [2] New connections: { $flatten\cpu.\exception_router.$procmux$804_Y [30:3] $flatten\cpu.\exception_router.$procmux$804_Y [1:0] } = 30'000000000000000000000000000000 Consolidated identical input bits for $mux cell $flatten\cpu.\exception_router.$procmux$812: Old ports: A={ 27'000000000000000000000000000 \cpu.decode.e_type [3] 1'0 \cpu.decode.e_type [1:0] }, B=31'0000000000000000000000000001011, Y=$flatten\cpu.\exception_router.$procmux$812_Y New ports: A={ \cpu.decode.e_type [3] \cpu.decode.e_type [1:0] }, B=3'111, Y={ $flatten\cpu.\exception_router.$procmux$812_Y [3] $flatten\cpu.\exception_router.$procmux$812_Y [1:0] } New connections: { $flatten\cpu.\exception_router.$procmux$812_Y [30:4] $flatten\cpu.\exception_router.$procmux$812_Y [2] } = 28'0000000000000000000000000000 Consolidated identical input bits for $mux cell $flatten\serial.\ser_internal.$procmux$566: Old ports: A={ 1'1 \serial.ser_internal.tx_shreg [9:1] }, B={ 1'1 \serial.ser_internal.tx_data 1'0 }, Y=$flatten\serial.\ser_internal.$procmux$566_Y New ports: A=\serial.ser_internal.tx_shreg [9:1], B={ \serial.ser_internal.tx_data 1'0 }, Y=$flatten\serial.\ser_internal.$procmux$566_Y [8:0] New connections: $flatten\serial.\ser_internal.$procmux$566_Y [9] = 1'1 Optimizing cells in module \top. Consolidated identical input bits for $mux cell $flatten\cpu.$procmux$649: Old ports: A=$flatten\cpu.$procmux$647_Y, B=4'0010, Y=$flatten\cpu.$procmux$649_Y New ports: A={ $flatten\cpu.$procmux$647_Y [3:2] 1'0 }, B=3'001, Y=$flatten\cpu.$procmux$649_Y [3:1] New connections: $flatten\cpu.$procmux$649_Y [0] = 1'0 Consolidated identical input bits for $mux cell $flatten\cpu.\decode.$procmux$1021: Old ports: A=2'10, B=$auto$wreduce.cc:461:run$1538 [1:0], Y=$flatten\cpu.\decode.$procmux$1021_Y [1:0] New ports: A=1'0, B=$auto$wreduce.cc:461:run$1538 [0], Y=$flatten\cpu.\decode.$procmux$1021_Y [0] New connections: $flatten\cpu.\decode.$procmux$1021_Y [1] = 1'1 Consolidated identical input bits for $mux cell $flatten\cpu.\exception_router.$procmux$808: Old ports: A=$flatten\cpu.\exception_router.$procmux$804_Y, B=31'0000000000000000000000000000110, Y=$flatten\cpu.\exception_router.$procmux$808_Y New ports: A={ $flatten\cpu.\exception_router.$procmux$804_Y [2] 1'0 }, B=2'11, Y=$flatten\cpu.\exception_router.$procmux$808_Y [2:1] New connections: { $flatten\cpu.\exception_router.$procmux$808_Y [30:3] $flatten\cpu.\exception_router.$procmux$808_Y [0] } = 29'00000000000000000000000000000 Optimizing cells in module \top. Consolidated identical input bits for $mux cell $flatten\cpu.\decode.$procmux$1023: Old ports: A=2'10, B=$flatten\cpu.\decode.$procmux$1021_Y [1:0], Y=$flatten\cpu.\decode.$procmux$1023_Y [1:0] New ports: A=1'0, B=$flatten\cpu.\decode.$procmux$1021_Y [0], Y=$flatten\cpu.\decode.$procmux$1023_Y [0] New connections: $flatten\cpu.\decode.$procmux$1023_Y [1] = 1'1 Consolidated identical input bits for $mux cell $flatten\cpu.\exception_router.$procmux$814: Old ports: A=$flatten\cpu.\exception_router.$procmux$808_Y, B=$flatten\cpu.\exception_router.$procmux$812_Y, Y=$flatten\cpu.\exception_router.$procmux$814_Y New ports: A={ 1'0 $flatten\cpu.\exception_router.$procmux$808_Y [2:1] 1'0 }, B={ $flatten\cpu.\exception_router.$procmux$812_Y [3] 1'0 $flatten\cpu.\exception_router.$procmux$812_Y [1:0] }, Y=$flatten\cpu.\exception_router.$procmux$814_Y [3:0] New connections: $flatten\cpu.\exception_router.$procmux$814_Y [30:4] = 27'000000000000000000000000000 Optimizing cells in module \top. Consolidated identical input bits for $mux cell $flatten\cpu.\decode.$procmux$1025: Old ports: A=2'10, B=$flatten\cpu.\decode.$procmux$1023_Y [1:0], Y=$flatten\cpu.\decode.$procmux$1025_Y [1:0] New ports: A=1'0, B=$flatten\cpu.\decode.$procmux$1023_Y [0], Y=$flatten\cpu.\decode.$procmux$1025_Y [0] New connections: $flatten\cpu.\decode.$procmux$1025_Y [1] = 1'1 Optimizing cells in module \top. Consolidated identical input bits for $mux cell $flatten\cpu.\decode.$procmux$1027: Old ports: A=$flatten\cpu.\decode.$procmux$1025_Y [1:0], B=2'10, Y=$flatten\cpu.\decode.$procmux$1027_Y [1:0] New ports: A=$flatten\cpu.\decode.$procmux$1025_Y [0], B=1'0, Y=$flatten\cpu.\decode.$procmux$1027_Y [0] New connections: $flatten\cpu.\decode.$procmux$1027_Y [1] = 1'1 Optimizing cells in module \top. Performed a total of 22 changes. 2.29.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 1 cells. 2.29.6. Executing OPT_DFF pass (perform DFF optimizations). Setting constant 0-bit at position 0 on $auto$ff.cc:266:slice$1424 ($sdffe) from module top. Setting constant 0-bit at position 1 on $auto$ff.cc:266:slice$1424 ($sdffe) from module top. Setting constant 0-bit at position 2 on $auto$ff.cc:266:slice$1424 ($sdffe) from module top. Setting constant 0-bit at position 4 on $auto$ff.cc:266:slice$1424 ($sdffe) from module top. Setting constant 0-bit at position 5 on $auto$ff.cc:266:slice$1424 ($sdffe) from module top. Setting constant 0-bit at position 6 on $auto$ff.cc:266:slice$1424 ($sdffe) from module top. Setting constant 0-bit at position 8 on $auto$ff.cc:266:slice$1424 ($sdffe) from module top. Setting constant 0-bit at position 9 on $auto$ff.cc:266:slice$1424 ($sdffe) from module top. Setting constant 0-bit at position 10 on $auto$ff.cc:266:slice$1424 ($sdffe) from module top. Setting constant 0-bit at position 13 on $auto$ff.cc:266:slice$1424 ($sdffe) from module top. Setting constant 0-bit at position 14 on $auto$ff.cc:266:slice$1424 ($sdffe) from module top. Setting constant 0-bit at position 15 on $auto$ff.cc:266:slice$1424 ($sdffe) from module top. Setting constant 0-bit at position 16 on $auto$ff.cc:266:slice$1424 ($sdffe) from module top. Setting constant 0-bit at position 17 on $auto$ff.cc:266:slice$1424 ($sdffe) from module top. Setting constant 0-bit at position 18 on $auto$ff.cc:266:slice$1424 ($sdffe) from module top. Setting constant 0-bit at position 19 on $auto$ff.cc:266:slice$1424 ($sdffe) from module top. Setting constant 0-bit at position 20 on $auto$ff.cc:266:slice$1424 ($sdffe) from module top. Setting constant 0-bit at position 21 on $auto$ff.cc:266:slice$1424 ($sdffe) from module top. Setting constant 0-bit at position 22 on $auto$ff.cc:266:slice$1424 ($sdffe) from module top. Setting constant 0-bit at position 23 on $auto$ff.cc:266:slice$1424 ($sdffe) from module top. Setting constant 0-bit at position 24 on $auto$ff.cc:266:slice$1424 ($sdffe) from module top. Setting constant 0-bit at position 25 on $auto$ff.cc:266:slice$1424 ($sdffe) from module top. Setting constant 0-bit at position 26 on $auto$ff.cc:266:slice$1424 ($sdffe) from module top. Setting constant 0-bit at position 27 on $auto$ff.cc:266:slice$1424 ($sdffe) from module top. Setting constant 0-bit at position 28 on $auto$ff.cc:266:slice$1424 ($sdffe) from module top. Setting constant 0-bit at position 29 on $auto$ff.cc:266:slice$1424 ($sdffe) from module top. Setting constant 0-bit at position 30 on $auto$ff.cc:266:slice$1424 ($sdffe) from module top. Setting constant 0-bit at position 31 on $auto$ff.cc:266:slice$1424 ($sdffe) from module top. 2.29.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 4 unused cells and 6 unused wires. 2.29.8. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 2.29.9. Rerunning OPT passes. (Maybe there is more to do..) 2.29.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 2.29.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 2.29.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 2.29.13. Executing OPT_DFF pass (perform DFF optimizations). Setting constant 1-bit at position 9 on $auto$ff.cc:266:slice$1322 ($sdffe) from module top. Setting constant 0-bit at position 4 on $auto$ff.cc:266:slice$1355 ($sdffe) from module top. Setting constant 0-bit at position 5 on $auto$ff.cc:266:slice$1355 ($sdffe) from module top. Setting constant 0-bit at position 6 on $auto$ff.cc:266:slice$1355 ($sdffe) from module top. Setting constant 0-bit at position 7 on $auto$ff.cc:266:slice$1355 ($sdffe) from module top. Setting constant 0-bit at position 8 on $auto$ff.cc:266:slice$1355 ($sdffe) from module top. Setting constant 0-bit at position 9 on $auto$ff.cc:266:slice$1355 ($sdffe) from module top. Setting constant 0-bit at position 10 on $auto$ff.cc:266:slice$1355 ($sdffe) from module top. Setting constant 0-bit at position 11 on $auto$ff.cc:266:slice$1355 ($sdffe) from module top. Setting constant 0-bit at position 12 on $auto$ff.cc:266:slice$1355 ($sdffe) from module top. Setting constant 0-bit at position 13 on $auto$ff.cc:266:slice$1355 ($sdffe) from module top. Setting constant 0-bit at position 14 on $auto$ff.cc:266:slice$1355 ($sdffe) from module top. Setting constant 0-bit at position 15 on $auto$ff.cc:266:slice$1355 ($sdffe) from module top. Setting constant 0-bit at position 16 on $auto$ff.cc:266:slice$1355 ($sdffe) from module top. Setting constant 0-bit at position 17 on $auto$ff.cc:266:slice$1355 ($sdffe) from module top. Setting constant 0-bit at position 18 on $auto$ff.cc:266:slice$1355 ($sdffe) from module top. Setting constant 0-bit at position 19 on $auto$ff.cc:266:slice$1355 ($sdffe) from module top. Setting constant 0-bit at position 20 on $auto$ff.cc:266:slice$1355 ($sdffe) from module top. Setting constant 0-bit at position 21 on $auto$ff.cc:266:slice$1355 ($sdffe) from module top. Setting constant 0-bit at position 22 on $auto$ff.cc:266:slice$1355 ($sdffe) from module top. Setting constant 0-bit at position 23 on $auto$ff.cc:266:slice$1355 ($sdffe) from module top. Setting constant 0-bit at position 24 on $auto$ff.cc:266:slice$1355 ($sdffe) from module top. Setting constant 0-bit at position 25 on $auto$ff.cc:266:slice$1355 ($sdffe) from module top. Setting constant 0-bit at position 26 on $auto$ff.cc:266:slice$1355 ($sdffe) from module top. Setting constant 0-bit at position 27 on $auto$ff.cc:266:slice$1355 ($sdffe) from module top. Setting constant 0-bit at position 28 on $auto$ff.cc:266:slice$1355 ($sdffe) from module top. Setting constant 0-bit at position 29 on $auto$ff.cc:266:slice$1355 ($sdffe) from module top. Setting constant 0-bit at position 30 on $auto$ff.cc:266:slice$1355 ($sdffe) from module top. Setting constant 0-bit at position 4 on $auto$ff.cc:266:slice$1422 ($sdff) from module top. 2.29.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 2.29.15. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 2.29.16. Rerunning OPT passes. (Maybe there is more to do..) 2.29.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 2.29.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 2.29.19. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 2.29.20. Executing OPT_DFF pass (perform DFF optimizations). 2.29.21. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 2.29.22. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 2.29.23. Finished OPT passes. (There is nothing left to do.) 2.30. Executing ICE40_WRAPCARRY pass (wrap carries). 2.31. Executing TECHMAP pass (map to technology primitives). 2.31.1. Executing Verilog-2005 frontend: /home/william/.local/bin/../share/yosys/techmap.v Parsing Verilog input from `/home/william/.local/bin/../share/yosys/techmap.v' to AST representation. Generating RTLIL representation for module `\_90_simplemap_bool_ops'. Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. Generating RTLIL representation for module `\_90_simplemap_logic_ops'. Generating RTLIL representation for module `\_90_simplemap_compare_ops'. Generating RTLIL representation for module `\_90_simplemap_various'. Generating RTLIL representation for module `\_90_simplemap_registers'. Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. Generating RTLIL representation for module `\_90_shift_shiftx'. Generating RTLIL representation for module `\_90_fa'. Generating RTLIL representation for module `\_90_lcu'. Generating RTLIL representation for module `\_90_alu'. Generating RTLIL representation for module `\_90_macc'. Generating RTLIL representation for module `\_90_alumacc'. Generating RTLIL representation for module `\$__div_mod_u'. Generating RTLIL representation for module `\$__div_mod_trunc'. Generating RTLIL representation for module `\_90_div'. Generating RTLIL representation for module `\_90_mod'. Generating RTLIL representation for module `\$__div_mod_floor'. Generating RTLIL representation for module `\_90_divfloor'. Generating RTLIL representation for module `\_90_modfloor'. Generating RTLIL representation for module `\_90_pow'. Generating RTLIL representation for module `\_90_pmux'. Generating RTLIL representation for module `\_90_demux'. Generating RTLIL representation for module `\_90_lut'. Successfully finished Verilog frontend. 2.31.2. Executing Verilog-2005 frontend: /home/william/.local/bin/../share/yosys/ice40/arith_map.v Parsing Verilog input from `/home/william/.local/bin/../share/yosys/ice40/arith_map.v' to AST representation. Generating RTLIL representation for module `\_80_ice40_alu'. Successfully finished Verilog frontend. 2.31.3. Continuing TECHMAP pass. Using extmapper simplemap for cells of type $or. Using extmapper simplemap for cells of type $ne. Using extmapper simplemap for cells of type $reduce_and. Using extmapper simplemap for cells of type $sdffe. Using extmapper simplemap for cells of type $mux. Using extmapper simplemap for cells of type $dffe. Using extmapper simplemap for cells of type $sdff. Using extmapper simplemap for cells of type $dff. Using extmapper simplemap for cells of type $not. Using extmapper simplemap for cells of type $reduce_or. Using extmapper simplemap for cells of type $eq. Using extmapper simplemap for cells of type $reduce_bool. Using template $paramod$c3cd1564c35d873179656addd6052d7ea8b6d991\_80_ice40_alu for cells of type $alu. Using extmapper simplemap for cells of type $lut. Using extmapper simplemap for cells of type $and. Using extmapper simplemap for cells of type $logic_not. Using template $paramod$fc16b9f758000d363d24f130038bd99b46b4fa1b\_90_pmux for cells of type $pmux. Using template $paramod$b098bc6f249c0ac91c4d6e19d54b23c285914115\_90_pmux for cells of type $pmux. Using template $paramod$e1270c504307e9914695c839a36c0c6fc6336d88\_90_pmux for cells of type $pmux. Using template $paramod$0ae36a7056fbae1b1191049d3533163e46c0843a\_90_pmux for cells of type $pmux. Using template $paramod$c5c783b17ab1d780abfad8cfe6563a0a7b47a3b0\_90_pmux for cells of type $pmux. Using template $paramod$aa21a8cfcdb2d038c61c16c25c37cdf209d597be\_90_pmux for cells of type $pmux. Using template $paramod$44a13d10af618e7fbe7b9aad2f6151ffcee1e2fa\_80_ice40_alu for cells of type $alu. Using template $paramod$d629d85c8826a74239b9178d1930215a43b0ceb0\_90_pmux for cells of type $pmux. Using template $paramod$645fe0cc96ae5edb83bff90cc2c78f4a20ca3e3c\_90_pmux for cells of type $pmux. Using extmapper simplemap for cells of type $xor. Using template $paramod$857150d3a9b7fb38b73bbaa31ff652415e553f98\_80_ice40_alu for cells of type $alu. Using template $paramod$fbc7873bff55778c0b3173955b7e4bce1d9d6834\_80_ice40_alu for cells of type $alu. Using template $paramod$80834bdd89ff0e27a02312429a7cc3a2e63489a8\_90_pmux for cells of type $pmux. Using template $paramod$c96def1cdcef2eee3c62e5dfb7ba2dd09c9f74dd\_90_pmux for cells of type $pmux. Using template $paramod$8fabc56b80a569262acfc42757a02ca0b8e91278\_90_pmux for cells of type $pmux. Using template $paramod$49f1dc3dcd6d2c748486fe94c6744a34a19bbafe\_90_pmux for cells of type $pmux. Using template $paramod$c2e415ef15bc3ccd2723772353a6b450d3d76206\_90_pmux for cells of type $pmux. Using template $paramod$8742280fdebca84e1c87f2a86ed84f62d558f4cc\_80_ice40_alu for cells of type $alu. Using template $paramod$d4fbf181fbf74ad2c33c84c81168c20bdbe88f93\_80_ice40_alu for cells of type $alu. Using template $paramod$3b7577489eb4433b1d5620cab7f3794743dee5ea\_80_ice40_alu for cells of type $alu. Using extmapper simplemap for cells of type $pos. No more expansions possible. 2.32. Executing OPT pass (performing simple optimizations). 2.32.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 2.32.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 427 cells. 2.32.3. Executing OPT_DFF pass (perform DFF optimizations). 2.32.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 152 unused cells and 1638 unused wires. 2.32.5. Finished fast OPT passes. 2.33. Executing ICE40_OPT pass (performing simple optimizations). 2.33.1. Running ICE40 specific optimizations. Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$1554.slice[0].carry: CO=\cd_sync.timer [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$1560.slice[32].carry: CO=$auto$alumacc.cc:485:replace_alu$1560.C [32] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$1563.slice[0].carry: CO=\cpu.control.sequencer.adr [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$1566.slice[0].carry: CO=\cpu.datapath.pc_mod.dat_r [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$1569.slice[0].carry: CO=\serial.ser_internal.tx_count [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$1572.slice[0].carry: CO=\serial.ser_internal.tx_phase [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$1575.slice[0].carry: CO=\serial.ser_internal.rx_count [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$1578.slice[0].carry: CO=\serial.ser_internal.rx_phase [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$1581.slice[0].carry: CO=\timer.prescalar [0] 2.33.2. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 2.33.3. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 2.33.4. Executing OPT_DFF pass (perform DFF optimizations). Adding SRST signal on $auto$ff.cc:266:slice$4166 ($_SDFF_PN0_) from module top (D = $flatten\cpu.\alu.$procmux$1219.Y_B [31], Q = \cpu.alu.data__o [31], rval = 1'0). Adding SRST signal on $auto$ff.cc:266:slice$4165 ($_SDFF_PN0_) from module top (D = $flatten\cpu.\alu.$procmux$1219.Y_B [30], Q = \cpu.alu.data__o [30], rval = 1'0). Adding SRST signal on $auto$ff.cc:266:slice$4164 ($_SDFF_PN0_) from module top (D = $flatten\cpu.\alu.$procmux$1219.Y_B [29], Q = \cpu.alu.data__o [29], rval = 1'0). Adding SRST signal on $auto$ff.cc:266:slice$4163 ($_SDFF_PN0_) from module top (D = $flatten\cpu.\alu.$procmux$1219.Y_B [28], Q = \cpu.alu.data__o [28], rval = 1'0). Adding SRST signal on $auto$ff.cc:266:slice$4162 ($_SDFF_PN0_) from module top (D = $flatten\cpu.\alu.$procmux$1219.Y_B [27], Q = \cpu.alu.data__o [27], rval = 1'0). Adding SRST signal on $auto$ff.cc:266:slice$4161 ($_SDFF_PN0_) from module top (D = $flatten\cpu.\alu.$procmux$1219.Y_B [26], Q = \cpu.alu.data__o [26], rval = 1'0). Adding SRST signal on $auto$ff.cc:266:slice$4160 ($_SDFF_PN0_) from module top (D = $flatten\cpu.\alu.$procmux$1219.Y_B [25], Q = \cpu.alu.data__o [25], rval = 1'0). Adding SRST signal on $auto$ff.cc:266:slice$4159 ($_SDFF_PN0_) from module top (D = $flatten\cpu.\alu.$procmux$1219.Y_B [24], Q = \cpu.alu.data__o [24], rval = 1'0). Adding SRST signal on $auto$ff.cc:266:slice$4158 ($_SDFF_PN0_) from module top (D = $flatten\cpu.\alu.$procmux$1219.Y_B [23], Q = \cpu.alu.data__o [23], rval = 1'0). Adding SRST signal on $auto$ff.cc:266:slice$4157 ($_SDFF_PN0_) from module top (D = $flatten\cpu.\alu.$procmux$1219.Y_B [22], Q = \cpu.alu.data__o [22], rval = 1'0). Adding SRST signal on $auto$ff.cc:266:slice$4156 ($_SDFF_PN0_) from module top (D = $flatten\cpu.\alu.$procmux$1219.Y_B [21], Q = \cpu.alu.data__o [21], rval = 1'0). Adding SRST signal on $auto$ff.cc:266:slice$4155 ($_SDFF_PN0_) from module top (D = $flatten\cpu.\alu.$procmux$1219.Y_B [20], Q = \cpu.alu.data__o [20], rval = 1'0). Adding SRST signal on $auto$ff.cc:266:slice$4154 ($_SDFF_PN0_) from module top (D = $flatten\cpu.\alu.$procmux$1219.Y_B [19], Q = \cpu.alu.data__o [19], rval = 1'0). Adding SRST signal on $auto$ff.cc:266:slice$4153 ($_SDFF_PN0_) from module top (D = $flatten\cpu.\alu.$procmux$1219.Y_B [18], Q = \cpu.alu.data__o [18], rval = 1'0). Adding SRST signal on $auto$ff.cc:266:slice$4152 ($_SDFF_PN0_) from module top (D = $flatten\cpu.\alu.$procmux$1219.Y_B [17], Q = \cpu.alu.data__o [17], rval = 1'0). Adding SRST signal on $auto$ff.cc:266:slice$4151 ($_SDFF_PN0_) from module top (D = $flatten\cpu.\alu.$procmux$1219.Y_B [16], Q = \cpu.alu.data__o [16], rval = 1'0). Adding SRST signal on $auto$ff.cc:266:slice$4150 ($_SDFF_PN0_) from module top (D = $flatten\cpu.\alu.$procmux$1219.Y_B [15], Q = \cpu.alu.data__o [15], rval = 1'0). Adding SRST signal on $auto$ff.cc:266:slice$4149 ($_SDFF_PN0_) from module top (D = $flatten\cpu.\alu.$procmux$1219.Y_B [14], Q = \cpu.alu.data__o [14], rval = 1'0). Adding SRST signal on $auto$ff.cc:266:slice$4148 ($_SDFF_PN0_) from module top (D = $flatten\cpu.\alu.$procmux$1219.Y_B [13], Q = \cpu.alu.data__o [13], rval = 1'0). Adding SRST signal on $auto$ff.cc:266:slice$4147 ($_SDFF_PN0_) from module top (D = $flatten\cpu.\alu.$procmux$1219.Y_B [12], Q = \cpu.alu.data__o [12], rval = 1'0). Adding SRST signal on $auto$ff.cc:266:slice$4146 ($_SDFF_PN0_) from module top (D = $flatten\cpu.\alu.$procmux$1219.Y_B [11], Q = \cpu.alu.data__o [11], rval = 1'0). Adding SRST signal on $auto$ff.cc:266:slice$4145 ($_SDFF_PN0_) from module top (D = $flatten\cpu.\alu.$procmux$1219.Y_B [10], Q = \cpu.alu.data__o [10], rval = 1'0). Adding SRST signal on $auto$ff.cc:266:slice$4144 ($_SDFF_PN0_) from module top (D = $flatten\cpu.\alu.$procmux$1219.Y_B [9], Q = \cpu.alu.data__o [9], rval = 1'0). Adding SRST signal on $auto$ff.cc:266:slice$4143 ($_SDFF_PN0_) from module top (D = $flatten\cpu.\alu.$procmux$1219.Y_B [8], Q = \cpu.alu.data__o [8], rval = 1'0). Adding SRST signal on $auto$ff.cc:266:slice$4142 ($_SDFF_PN0_) from module top (D = $flatten\cpu.\alu.$procmux$1219.Y_B [7], Q = \cpu.alu.data__o [7], rval = 1'0). Adding SRST signal on $auto$ff.cc:266:slice$4141 ($_SDFF_PN0_) from module top (D = $flatten\cpu.\alu.$procmux$1219.Y_B [6], Q = \cpu.alu.data__o [6], rval = 1'0). Adding SRST signal on $auto$ff.cc:266:slice$4140 ($_SDFF_PN0_) from module top (D = $flatten\cpu.\alu.$procmux$1219.Y_B [5], Q = \cpu.alu.data__o [5], rval = 1'0). Adding SRST signal on $auto$ff.cc:266:slice$4139 ($_SDFF_PN0_) from module top (D = $flatten\cpu.\alu.$procmux$1219.Y_B [4], Q = \cpu.alu.data__o [4], rval = 1'0). Adding SRST signal on $auto$ff.cc:266:slice$4138 ($_SDFF_PN0_) from module top (D = $flatten\cpu.\alu.$procmux$1219.Y_B [3], Q = \cpu.alu.data__o [3], rval = 1'0). Adding SRST signal on $auto$ff.cc:266:slice$4137 ($_SDFF_PN0_) from module top (D = $flatten\cpu.\alu.$procmux$1219.Y_B [2], Q = \cpu.alu.data__o [2], rval = 1'0). Adding SRST signal on $auto$ff.cc:266:slice$4136 ($_SDFF_PN0_) from module top (D = $flatten\cpu.\alu.$procmux$1219.Y_B [1], Q = \cpu.alu.data__o [1], rval = 1'0). 2.33.5. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 31 unused cells and 32 unused wires. 2.33.6. Rerunning OPT passes. (Removed registers in this run.) 2.33.7. Running ICE40 specific optimizations. 2.33.8. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 2.33.9. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 30 cells. 2.33.10. Executing OPT_DFF pass (perform DFF optimizations). 2.33.11. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 0 unused cells and 30 unused wires. 2.33.12. Rerunning OPT passes. (Removed registers in this run.) 2.33.13. Running ICE40 specific optimizations. 2.33.14. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 2.33.15. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 2.33.16. Executing OPT_DFF pass (perform DFF optimizations). 2.33.17. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 2.33.18. Finished OPT passes. (There is nothing left to do.) 2.34. Executing DFFLEGALIZE pass (convert FFs to types supported by the target). 2.35. Executing TECHMAP pass (map to technology primitives). 2.35.1. Executing Verilog-2005 frontend: /home/william/.local/bin/../share/yosys/ice40/ff_map.v Parsing Verilog input from `/home/william/.local/bin/../share/yosys/ice40/ff_map.v' to AST representation. Generating RTLIL representation for module `\$_DFF_N_'. Generating RTLIL representation for module `\$_DFF_P_'. Generating RTLIL representation for module `\$_DFFE_NP_'. Generating RTLIL representation for module `\$_DFFE_PP_'. Generating RTLIL representation for module `\$_DFF_NP0_'. Generating RTLIL representation for module `\$_DFF_NP1_'. Generating RTLIL representation for module `\$_DFF_PP0_'. Generating RTLIL representation for module `\$_DFF_PP1_'. Generating RTLIL representation for module `\$_DFFE_NP0P_'. Generating RTLIL representation for module `\$_DFFE_NP1P_'. Generating RTLIL representation for module `\$_DFFE_PP0P_'. Generating RTLIL representation for module `\$_DFFE_PP1P_'. Generating RTLIL representation for module `\$_SDFF_NP0_'. Generating RTLIL representation for module `\$_SDFF_NP1_'. Generating RTLIL representation for module `\$_SDFF_PP0_'. Generating RTLIL representation for module `\$_SDFF_PP1_'. Generating RTLIL representation for module `\$_SDFFCE_NP0P_'. Generating RTLIL representation for module `\$_SDFFCE_NP1P_'. Generating RTLIL representation for module `\$_SDFFCE_PP0P_'. Generating RTLIL representation for module `\$_SDFFCE_PP1P_'. Successfully finished Verilog frontend. 2.35.2. Continuing TECHMAP pass. Using template \$_SDFFCE_PP0P_ for cells of type $_SDFFCE_PP0P_. Using template \$_SDFF_PP0_ for cells of type $_SDFF_PP0_. Using template \$_DFFE_PP_ for cells of type $_DFFE_PP_. Using template \$_DFF_P_ for cells of type $_DFF_P_. No more expansions possible. 2.36. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 2.37. Executing SIMPLEMAP pass (map simple cells to gate primitives). Mapping top.$auto$alumacc.cc:485:replace_alu$1554.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$1560.slice[32].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$1563.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$1566.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$1569.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$1572.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$1575.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$1578.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$1581.slice[0].carry ($lut). 2.38. Executing ICE40_OPT pass (performing simple optimizations). 2.38.1. Running ICE40 specific optimizations. 2.38.2. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 2.38.3. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 635 cells. 2.38.4. Executing OPT_DFF pass (perform DFF optimizations). 2.38.5. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 2 unused cells and 3245 unused wires. 2.38.6. Rerunning OPT passes. (Removed registers in this run.) 2.38.7. Running ICE40 specific optimizations. 2.38.8. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 2.38.9. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 2.38.10. Executing OPT_DFF pass (perform DFF optimizations). 2.38.11. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 2.38.12. Rerunning OPT passes. (Removed registers in this run.) 2.38.13. Running ICE40 specific optimizations. 2.38.14. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 2.38.15. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 2.38.16. Executing OPT_DFF pass (perform DFF optimizations). 2.38.17. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 2.38.18. Finished OPT passes. (There is nothing left to do.) 2.39. Executing TECHMAP pass (map to technology primitives). 2.39.1. Executing Verilog-2005 frontend: /home/william/.local/bin/../share/yosys/ice40/latches_map.v Parsing Verilog input from `/home/william/.local/bin/../share/yosys/ice40/latches_map.v' to AST representation. Generating RTLIL representation for module `\$_DLATCH_N_'. Generating RTLIL representation for module `\$_DLATCH_P_'. Successfully finished Verilog frontend. 2.39.2. Continuing TECHMAP pass. No more expansions possible. 2.40. Executing Verilog-2005 frontend: /home/william/.local/bin/../share/yosys/ice40/abc9_model.v Parsing Verilog input from `/home/william/.local/bin/../share/yosys/ice40/abc9_model.v' to AST representation. Generating RTLIL representation for module `$__ICE40_CARRY_WRAPPER'. Successfully finished Verilog frontend. 2.41. Executing ABC9 pass. 2.41.1. Executing ABC9_OPS pass (helper functions for ABC9). 2.41.2. Executing ABC9_OPS pass (helper functions for ABC9). 2.41.3. Executing SCC pass (detecting logic loops). Found 0 SCCs in module top. Found 0 SCCs. 2.41.4. Executing ABC9_OPS pass (helper functions for ABC9). 2.41.5. Executing PROC pass (convert processes to netlists). 2.41.5.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 2.41.5.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 2.41.5.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 0 assignments to connections. 2.41.5.4. Executing PROC_INIT pass (extract init attributes). 2.41.5.5. Executing PROC_ARST pass (detect async resets in processes). 2.41.5.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 2.41.5.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2.41.5.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2.41.5.9. Executing PROC_DFF pass (convert process syncs to FFs). 2.41.5.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2.41.5.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 2.41.5.12. Executing OPT_EXPR pass (perform const folding). 2.41.6. Executing TECHMAP pass (map to technology primitives). 2.41.6.1. Executing Verilog-2005 frontend: /home/william/.local/bin/../share/yosys/techmap.v Parsing Verilog input from `/home/william/.local/bin/../share/yosys/techmap.v' to AST representation. Generating RTLIL representation for module `\_90_simplemap_bool_ops'. Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. Generating RTLIL representation for module `\_90_simplemap_logic_ops'. Generating RTLIL representation for module `\_90_simplemap_compare_ops'. Generating RTLIL representation for module `\_90_simplemap_various'. Generating RTLIL representation for module `\_90_simplemap_registers'. Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. Generating RTLIL representation for module `\_90_shift_shiftx'. Generating RTLIL representation for module `\_90_fa'. Generating RTLIL representation for module `\_90_lcu'. Generating RTLIL representation for module `\_90_alu'. Generating RTLIL representation for module `\_90_macc'. Generating RTLIL representation for module `\_90_alumacc'. Generating RTLIL representation for module `\$__div_mod_u'. Generating RTLIL representation for module `\$__div_mod_trunc'. Generating RTLIL representation for module `\_90_div'. Generating RTLIL representation for module `\_90_mod'. Generating RTLIL representation for module `\$__div_mod_floor'. Generating RTLIL representation for module `\_90_divfloor'. Generating RTLIL representation for module `\_90_modfloor'. Generating RTLIL representation for module `\_90_pow'. Generating RTLIL representation for module `\_90_pmux'. Generating RTLIL representation for module `\_90_demux'. Generating RTLIL representation for module `\_90_lut'. Successfully finished Verilog frontend. 2.41.6.2. Continuing TECHMAP pass. Using extmapper simplemap for cells of type $logic_not. Using extmapper simplemap for cells of type $mux. Using extmapper simplemap for cells of type $dff. Using extmapper simplemap for cells of type $logic_and. No more expansions possible. 2.41.7. Executing OPT pass (performing simple optimizations). 2.41.7.1. Executing OPT_EXPR pass (perform const folding). Optimizing module SB_DFF. Optimizing module SB_DFFE. Optimizing module SB_DFFESR. Optimizing module SB_DFFSR. 2.41.7.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\SB_DFF'. Finding identical cells in module `\SB_DFFE'. Finding identical cells in module `\SB_DFFESR'. Finding identical cells in module `\SB_DFFSR'. Removed a total of 2 cells. 2.41.7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \SB_DFF.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module \SB_DFFE.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module \SB_DFFESR.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module \SB_DFFSR.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 2.41.7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \SB_DFF. Optimizing cells in module \SB_DFFE. Optimizing cells in module \SB_DFFESR. Optimizing cells in module \SB_DFFSR. Performed a total of 0 changes. 2.41.7.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\SB_DFF'. Finding identical cells in module `\SB_DFFE'. Finding identical cells in module `\SB_DFFESR'. Finding identical cells in module `\SB_DFFSR'. Removed a total of 0 cells. 2.41.7.6. Executing OPT_DFF pass (perform DFF optimizations). 2.41.7.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \SB_DFF.. Finding unused cells or wires in module \SB_DFFE.. Finding unused cells or wires in module \SB_DFFESR.. Finding unused cells or wires in module \SB_DFFSR.. Removed 0 unused cells and 14 unused wires. 2.41.7.8. Executing OPT_EXPR pass (perform const folding). Optimizing module SB_DFF. Optimizing module SB_DFFE. Optimizing module SB_DFFESR. Optimizing module SB_DFFSR. 2.41.7.9. Rerunning OPT passes. (Maybe there is more to do..) 2.41.7.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \SB_DFF.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module \SB_DFFE.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module \SB_DFFESR.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module \SB_DFFSR.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 2.41.7.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \SB_DFF. Optimizing cells in module \SB_DFFE. Optimizing cells in module \SB_DFFESR. Optimizing cells in module \SB_DFFSR. Performed a total of 0 changes. 2.41.7.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\SB_DFF'. Finding identical cells in module `\SB_DFFE'. Finding identical cells in module `\SB_DFFESR'. Finding identical cells in module `\SB_DFFSR'. Removed a total of 0 cells. 2.41.7.13. Executing OPT_DFF pass (perform DFF optimizations). 2.41.7.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \SB_DFF.. Finding unused cells or wires in module \SB_DFFE.. Finding unused cells or wires in module \SB_DFFESR.. Finding unused cells or wires in module \SB_DFFSR.. 2.41.7.15. Executing OPT_EXPR pass (perform const folding). Optimizing module SB_DFF. Optimizing module SB_DFFE. Optimizing module SB_DFFESR. Optimizing module SB_DFFSR. 2.41.7.16. Finished OPT passes. (There is nothing left to do.) 2.41.8. Executing ABC9_OPS pass (helper functions for ABC9). 2.41.9. Executing SUBMOD pass (moving cells to submodules as requested). 2.41.9.1. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \SB_DFF.. Finding unused cells or wires in module \SB_DFFE.. Finding unused cells or wires in module \SB_DFFESR.. Finding unused cells or wires in module \SB_DFFSR.. 2.41.9.2. Continuing SUBMOD pass. Creating submodule $abc9_flop (\SB_DFF_$abc9_flop) of module \SB_DFF. signal $auto$abc9_ops.cc:506:prep_dff_submod$12023: output \n1 signal \D: input \D signal \C: input \C signal \Q: input \Q cell $specify$9 ($specify3) cell $specify$8 ($specrule) cell $auto$abc9_ops.cc:507:prep_dff_submod$12024 ($_MUX_) Creating submodule $abc9_flop (\SB_DFFE_$abc9_flop) of module \SB_DFFE. signal $auto$abc9_ops.cc:506:prep_dff_submod$12025: output \n1 signal \Q: input \Q signal $0\Q[0:0]: internal signal \D: input \D signal \C: input \C signal \E: input \E cell $specify$12 ($specify3) cell $specify$11 ($specrule) cell $specify$10 ($specrule) cell $auto$simplemap.cc:267:simplemap_mux$12020 ($_MUX_) cell $auto$abc9_ops.cc:507:prep_dff_submod$12026 ($_MUX_) Creating submodule $abc9_flop (\SB_DFFESR_$abc9_flop) of module \SB_DFFESR. signal \D: input \D signal $auto$abc9_ops.cc:506:prep_dff_submod$12027: output \n1 signal \Q: input \Q signal $logic_not$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:612$186_Y: internal signal \E: input \E signal \C: input \C signal $logic_and$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:618$188_Y: internal signal $logic_and$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:612$187_Y: internal signal \R: input \R signal $procmux$417_Y: internal signal $0\Q[0:0]: internal cell $specify$33 ($specify3) cell $specify$32 ($specify3) cell $specify$31 ($specrule) cell $specify$30 ($specrule) cell $specify$29 ($specrule) cell $auto$simplemap.cc:267:simplemap_mux$12018 ($_MUX_) cell $auto$simplemap.cc:267:simplemap_mux$12017 ($_MUX_) cell $auto$simplemap.cc:225:simplemap_logbin$12016 ($_AND_) cell $auto$simplemap.cc:225:simplemap_logbin$12014 ($_AND_) cell $auto$simplemap.cc:196:simplemap_lognot$12012 ($_NOT_) cell $auto$abc9_ops.cc:507:prep_dff_submod$12028 ($_MUX_) Creating submodule $abc9_flop (\SB_DFFSR_$abc9_flop) of module \SB_DFFSR. signal $logic_not$/home/william/.local/bin/../share/yosys/ice40/cells_sim.v:370$174_Y: internal signal $auto$abc9_ops.cc:506:prep_dff_submod$12029: output \n1 signal \C: input \C signal \D: input \D signal \R: input \R signal \Q: input \Q signal $0\Q[0:0]: internal cell $specify$16 ($specify3) cell $specify$15 ($specify3) cell $specify$14 ($specrule) cell $specify$13 ($specrule) cell $auto$simplemap.cc:267:simplemap_mux$12010 ($_MUX_) cell $auto$simplemap.cc:196:simplemap_lognot$12009 ($_NOT_) cell $auto$abc9_ops.cc:507:prep_dff_submod$12030 ($_MUX_) 2.41.9.3. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \SB_DFFSR_$abc9_flop.. Finding unused cells or wires in module \SB_DFFESR_$abc9_flop.. Finding unused cells or wires in module \SB_DFFE_$abc9_flop.. Finding unused cells or wires in module \SB_DFF_$abc9_flop.. Finding unused cells or wires in module \SB_DFF.. Finding unused cells or wires in module \SB_DFFE.. Finding unused cells or wires in module \SB_DFFESR.. Finding unused cells or wires in module \SB_DFFSR.. Removed 0 unused cells and 8 unused wires. Renaming cell SB_DFF_$abc9_flop to _TECHMAP_REPLACE_ in module SB_DFF. Renaming cell SB_DFFE_$abc9_flop to _TECHMAP_REPLACE_ in module SB_DFFE. Renaming cell SB_DFFESR_$abc9_flop to _TECHMAP_REPLACE_ in module SB_DFFESR. Renaming cell SB_DFFSR_$abc9_flop to _TECHMAP_REPLACE_ in module SB_DFFSR. 2.41.10. Executing ABC9_OPS pass (helper functions for ABC9). 2.41.11. Executing TECHMAP pass (map to technology primitives). 2.41.11.1. Executing Verilog-2005 frontend: /home/william/.local/bin/../share/yosys/abc9_map.v Parsing Verilog input from `/home/william/.local/bin/../share/yosys/abc9_map.v' to AST representation. Generating RTLIL representation for module `\$_DFF_x_'. Successfully finished Verilog frontend. 2.41.11.2. Continuing TECHMAP pass. Using template SB_DFFSR for cells of type SB_DFFSR. Using template SB_DFFESR for cells of type SB_DFFESR. Using template SB_DFFE for cells of type SB_DFFE. Using template SB_DFF for cells of type SB_DFF. No more expansions possible. 2.41.12. Executing Verilog-2005 frontend: /home/william/.local/bin/../share/yosys/abc9_model.v Parsing Verilog input from `/home/william/.local/bin/../share/yosys/abc9_model.v' to AST representation. Generating RTLIL representation for module `$__ABC9_DELAY'. Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'. Generating RTLIL representation for module `$__DFF_N__$abc9_flop'. Generating RTLIL representation for module `$__DFF_P__$abc9_flop'. Successfully finished Verilog frontend. 2.41.13. Executing ABC9_OPS pass (helper functions for ABC9). 2.41.14. Executing ABC9_OPS pass (helper functions for ABC9). 2.41.15. Executing ABC9_OPS pass (helper functions for ABC9). 2.41.16. Executing TECHMAP pass (map to technology primitives). 2.41.16.1. Executing Verilog-2005 frontend: /home/william/.local/bin/../share/yosys/techmap.v Parsing Verilog input from `/home/william/.local/bin/../share/yosys/techmap.v' to AST representation. Generating RTLIL representation for module `\_90_simplemap_bool_ops'. Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. Generating RTLIL representation for module `\_90_simplemap_logic_ops'. Generating RTLIL representation for module `\_90_simplemap_compare_ops'. Generating RTLIL representation for module `\_90_simplemap_various'. Generating RTLIL representation for module `\_90_simplemap_registers'. Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. Generating RTLIL representation for module `\_90_shift_shiftx'. Generating RTLIL representation for module `\_90_fa'. Generating RTLIL representation for module `\_90_lcu'. Generating RTLIL representation for module `\_90_alu'. Generating RTLIL representation for module `\_90_macc'. Generating RTLIL representation for module `\_90_alumacc'. Generating RTLIL representation for module `\$__div_mod_u'. Generating RTLIL representation for module `\$__div_mod_trunc'. Generating RTLIL representation for module `\_90_div'. Generating RTLIL representation for module `\_90_mod'. Generating RTLIL representation for module `\$__div_mod_floor'. Generating RTLIL representation for module `\_90_divfloor'. Generating RTLIL representation for module `\_90_modfloor'. Generating RTLIL representation for module `\_90_pow'. Generating RTLIL representation for module `\_90_pmux'. Generating RTLIL representation for module `\_90_demux'. Generating RTLIL representation for module `\_90_lut'. Successfully finished Verilog frontend. 2.41.16.2. Continuing TECHMAP pass. Using template $paramod$__ICE40_CARRY_WRAPPER\LUT=16'0110100110010110\I3_IS_CI=1'1 for cells of type $paramod$__ICE40_CARRY_WRAPPER\LUT=16'0110100110010110\I3_IS_CI=1'1. Using template SB_DFFESR_$abc9_flop for cells of type SB_DFFESR_$abc9_flop. Using template SB_DFFE_$abc9_flop for cells of type SB_DFFE_$abc9_flop. Using template SB_DFFSR_$abc9_flop for cells of type SB_DFFSR_$abc9_flop. Using template SB_DFF_$abc9_flop for cells of type SB_DFF_$abc9_flop. Using template $paramod\SB_LUT4\LUT_INIT=16'0110100110010110 for cells of type SB_LUT4. Using template SB_CARRY for cells of type SB_CARRY. Using extmapper simplemap for cells of type $mux. Using extmapper simplemap for cells of type $logic_and. Using extmapper simplemap for cells of type $logic_or. No more expansions possible. 2.41.17. Executing OPT pass (performing simple optimizations). 2.41.17.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 2.41.17.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 15 cells. 2.41.17.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 2.41.17.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 2.41.17.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 2.41.17.6. Executing OPT_DFF pass (perform DFF optimizations). 2.41.17.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 0 unused cells and 52 unused wires. 2.41.17.8. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 2.41.17.9. Rerunning OPT passes. (Maybe there is more to do..) 2.41.17.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 2.41.17.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 2.41.17.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 2.41.17.13. Executing OPT_DFF pass (perform DFF optimizations). 2.41.17.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 2.41.17.15. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 2.41.17.16. Finished OPT passes. (There is nothing left to do.) 2.41.18. Executing AIGMAP pass (map logic to AIG). Module top: replaced 11 cells with 71 new cells, skipped 26 cells. replaced 2 cell types: 2 $_OR_ 9 $_MUX_ not replaced 5 cell types: 8 $specify2 6 $specify3 6 $specrule 2 $_NOT_ 4 $_AND_ 2.41.19. Executing AIGMAP pass (map logic to AIG). Module top: replaced 1797 cells with 9094 new cells, skipped 3267 cells. replaced 4 cell types: 1123 $_OR_ 39 $_XOR_ 29 $_ORNOT_ 606 $_MUX_ not replaced 31 cell types: 250 $_NOT_ 1115 $_AND_ 456 $_DFF_P_ 1 $paramod$d7fa99ee938258c62bd3b967ba8ba7f9e6861f52\SB_RAM40_4K 1 $paramod$c45611040bf4290b562e860e640d907d8fb59335\SB_RAM40_4K 1 $paramod$8892e089f621ee819771b0f7924e6bdb2743ebf0\SB_RAM40_4K 1 $paramod$9ea9987117d84344c37925ae040e244a6b19da90\SB_RAM40_4K 16 SB_IO 1 SB_GB_IO 147 $paramod$__ICE40_CARRY_WRAPPER\LUT=16'0110100110010110\I3_IS_CI=1'1 1 $paramod$0e9d59b0aa529313fb470eb883d3681c14cbd533\SB_RAM40_4K 1 $paramod$d1e07e07d74ca83c508e886c73cf8e7216ce4f9a\SB_RAM40_4K 224 $paramod$__ABC9_DELAY\DELAY=32'00000000000000000000000010100001 14 $paramod$__ABC9_DELAY\DELAY=32'00000000000000000000000010000101 84 SB_DFFSR_$abc9_flop 80 SB_DFFE_$abc9_flop 290 SB_DFFESR_$abc9_flop 2 SB_DFF_$abc9_flop 1 $paramod$26b98585bf827a2bf7ebac094a246d8dc7d635ba\SB_RAM40_4K 154 $paramod$__ABC9_DELAY\DELAY=32'00000000000000000000000011001011 1 $paramod$00e1043b4ea9201c229bdad53af82923c0fb958e\SB_RAM40_4K 1 $paramod$a44885463885622fd2f6f8d633534558c4ea16ad\SB_RAM40_4K 1 $paramod$1729377dbe7e7c55381029ab14e98a3254b820de\SB_RAM40_4K 1 $paramod$b2f76ebf376d4161fac9811f3d1d081eec373a8c\SB_RAM40_4K 28 $paramod$__ABC9_DELAY\DELAY=32'00000000000000000000000100001011 154 $paramod$__ABC9_DELAY\DELAY=32'00000000000000000000000011100000 14 $paramod$__ABC9_DELAY\DELAY=32'00000000000000000000000001100010 1 $paramod$cc7ca8e18e7411e7645309671c4dfe65ebd58281\SB_RAM40_4K 1 $paramod$b7274ee03d5bce333b8e1f04596dfacf63550bf2\SB_RAM40_4K 1 $paramod$0be788f7e7503dc1ce265f93d57fe05b8fa23cd5\SB_RAM40_4K 224 $paramod$__ABC9_DELAY\DELAY=32'00000000000000000000000100010010 2.41.19.1. Executing ABC9_OPS pass (helper functions for ABC9). 2.41.19.2. Executing ABC9_OPS pass (helper functions for ABC9). 2.41.19.3. Executing XAIGER backend. Extracted 4202 AND gates and 13130 wires from module `top' to a netlist network with 135 inputs and 836 outputs. 2.41.19.4. Executing ABC9_EXE pass (technology mapping using ABC9). 2.41.19.5. Executing ABC9. Running ABC command: "/yosys-abc" -s -f /abc.script 2>&1 ABC: ABC command line: "source /abc.script". ABC: ABC: + read_lut /input.lut ABC: + read_box /input.box ABC: + &read /input.xaig ABC: + &ps ABC: /input : i/o = 135/ 836 boxff =456(1) and = 3793 lev = 54 (2.00) mem = 0.15 MB box = 959 bb = 812 ABC: + &scorr ABC: + &sweep ABC: + &if -W 250 -D 83333 ABC: + &save ABC: + &st ABC: + &syn2 ABC: + &if -W 250 -D 83333 -v ABC: K = 4. Memory (bytes): Truth = 0. Cut = 48. Obj = 128. Set = 528. CutMin = no ABC: Node = 2660. Ch = 0. Total mem = 1.31 MB. Peak cut mem = 0.06 MB. ABC: P: Del = 83333.00. Ar = 1305.0. Edge = 4719. Cut = 14252. T = 0.00 sec ABC: P: Del = 83333.00. Ar = 1277.0. Edge = 4712. Cut = 14096. T = 0.00 sec ABC: P: Del = 83333.00. Ar = 1067.0. Edge = 3616. Cut = 14383. T = 0.00 sec ABC: E: Del = 83333.00. Ar = 1066.0. Edge = 3615. Cut = 14383. T = 0.00 sec ABC: F: Del = 83333.00. Ar = 1066.0. Edge = 3631. Cut = 14408. T = 0.00 sec ABC: E: Del = 83333.00. Ar = 1063.0. Edge = 3623. Cut = 14408. T = 0.00 sec ABC: A: Del = 83333.00. Ar = 1063.0. Edge = 3486. Cut = 14483. T = 0.00 sec ABC: E: Del = 83333.00. Ar = 1063.0. Edge = 3486. Cut = 14483. T = 0.00 sec ABC: A: Del = 83333.00. Ar = 1063.0. Edge = 3486. Cut = 14483. T = 0.00 sec ABC: E: Del = 83333.00. Ar = 1063.0. Edge = 3486. Cut = 14483. T = 0.00 sec ABC: Total time = 0.02 sec ABC: + &save ABC: + &load ABC: + &st ABC: + &if -g -K 6 ABC: + &dch -f ABC: + &if -W 250 -D 83333 -v ABC: K = 4. Memory (bytes): Truth = 0. Cut = 48. Obj = 128. Set = 528. CutMin = no ABC: Node = 4453. Ch = 516. Total mem = 1.55 MB. Peak cut mem = 0.07 MB. ABC: P: Del = 83333.00. Ar = 1372.0. Edge = 4960. Cut = 27544. T = 0.01 sec ABC: P: Del = 83333.00. Ar = 1264.0. Edge = 4690. Cut = 26461. T = 0.01 sec ABC: P: Del = 83333.00. Ar = 1037.0. Edge = 3632. Cut = 28436. T = 0.01 sec ABC: F: Del = 83333.00. Ar = 1026.0. Edge = 3571. Cut = 29032. T = 0.01 sec ABC: A: Del = 83333.00. Ar = 980.0. Edge = 3338. Cut = 28829. T = 0.01 sec ABC: A: Del = 83333.00. Ar = 978.0. Edge = 3335. Cut = 28718. T = 0.01 sec ABC: Total time = 0.04 sec ABC: + &save ABC: + &load ABC: + &st ABC: + &if -g -K 6 ABC: + &synch2 ABC: + &if -W 250 -D 83333 -v ABC: K = 4. Memory (bytes): Truth = 0. Cut = 48. Obj = 128. Set = 528. CutMin = no ABC: Node = 3700. Ch = 328. Total mem = 1.45 MB. Peak cut mem = 0.07 MB. ABC: P: Del = 83333.00. Ar = 1407.0. Edge = 5049. Cut = 21364. T = 0.00 sec ABC: P: Del = 83333.00. Ar = 1304.0. Edge = 4823. Cut = 20547. T = 0.00 sec ABC: P: Del = 83333.00. Ar = 1035.0. Edge = 3587. Cut = 22213. T = 0.00 sec ABC: F: Del = 83333.00. Ar = 1008.0. Edge = 3536. Cut = 22530. T = 0.00 sec ABC: A: Del = 83333.00. Ar = 987.0. Edge = 3356. Cut = 22487. T = 0.01 sec ABC: A: Del = 83333.00. Ar = 986.0. Edge = 3353. Cut = 22466. T = 0.01 sec ABC: Total time = 0.03 sec ABC: + &save ABC: + &load ABC: + &write -n /output.aig ABC: + &mfs ABC: + &ps -l ABC: /input : i/o = 135/ 836 boxff =419(1) and = 2639 lev = 32 (1.60) mem = 0.14 MB box = 959 bb = 812 ABC: Mapping (K=4) : lut = 960 edge = 3244 lev = 20 (0.95) levB = 36 mem = 0.06 MB ABC: LUT = 960 : 2=157 16.4 % 3=282 29.4 % 4=521 54.3 % Ave = 3.38 ABC: + &write -n /output.aig ABC: + time ABC: elapse: 1.73 seconds, total: 1.73 seconds 2.41.19.6. Executing AIGER frontend. Removed 3516 unused cells and 10476 unused wires. 2.41.19.7. Executing ABC9_OPS pass (helper functions for ABC9). ABC RESULTS: $lut cells: 1005 ABC RESULTS: $paramod$__ICE40_CARRY_WRAPPER\LUT=16'0110100110010110\I3_IS_CI=1'1 cells: 147 ABC RESULTS: \SB_DFFSR_$abc9_flop cells: 84 ABC RESULTS: \SB_DFFE_$abc9_flop cells: 44 ABC RESULTS: \SB_DFFESR_$abc9_flop cells: 290 ABC RESULTS: \SB_DFF_$abc9_flop cells: 1 ABC RESULTS: input signals: 7 ABC RESULTS: output signals: 833 Removing temp directory. 2.41.20. Executing TECHMAP pass (map to technology primitives). 2.41.20.1. Executing Verilog-2005 frontend: /home/william/.local/bin/../share/yosys/abc9_unmap.v Parsing Verilog input from `/home/william/.local/bin/../share/yosys/abc9_unmap.v' to AST representation. Generating RTLIL representation for module `\$__DFF_x__$abc9_flop'. Generating RTLIL representation for module `\$__ABC9_SCC_BREAKER'. Successfully finished Verilog frontend. 2.41.20.2. Continuing TECHMAP pass. Using template SB_DFFESR_$abc9_flop for cells of type SB_DFFESR_$abc9_flop. Using template SB_DFFSR_$abc9_flop for cells of type SB_DFFSR_$abc9_flop. Using template SB_DFF_$abc9_flop for cells of type SB_DFF_$abc9_flop. Using template SB_DFFE_$abc9_flop for cells of type SB_DFFE_$abc9_flop. Using template $paramod$__ICE40_CARRY_WRAPPER\LUT=16'0110100110010110\I3_IS_CI=1'1 for cells of type $paramod$__ICE40_CARRY_WRAPPER\LUT=16'0110100110010110\I3_IS_CI=1'1. Using template $paramod$9ea9987117d84344c37925ae040e244a6b19da90\SB_RAM40_4K for cells of type $paramod$9ea9987117d84344c37925ae040e244a6b19da90\SB_RAM40_4K. Using template $paramod$1729377dbe7e7c55381029ab14e98a3254b820de\SB_RAM40_4K for cells of type $paramod$1729377dbe7e7c55381029ab14e98a3254b820de\SB_RAM40_4K. Using template $paramod$26b98585bf827a2bf7ebac094a246d8dc7d635ba\SB_RAM40_4K for cells of type $paramod$26b98585bf827a2bf7ebac094a246d8dc7d635ba\SB_RAM40_4K. Using template $paramod$8892e089f621ee819771b0f7924e6bdb2743ebf0\SB_RAM40_4K for cells of type $paramod$8892e089f621ee819771b0f7924e6bdb2743ebf0\SB_RAM40_4K. Using template $paramod$a44885463885622fd2f6f8d633534558c4ea16ad\SB_RAM40_4K for cells of type $paramod$a44885463885622fd2f6f8d633534558c4ea16ad\SB_RAM40_4K. Using template $paramod$00e1043b4ea9201c229bdad53af82923c0fb958e\SB_RAM40_4K for cells of type $paramod$00e1043b4ea9201c229bdad53af82923c0fb958e\SB_RAM40_4K. Using template $paramod$d7fa99ee938258c62bd3b967ba8ba7f9e6861f52\SB_RAM40_4K for cells of type $paramod$d7fa99ee938258c62bd3b967ba8ba7f9e6861f52\SB_RAM40_4K. Using template $paramod$cc7ca8e18e7411e7645309671c4dfe65ebd58281\SB_RAM40_4K for cells of type $paramod$cc7ca8e18e7411e7645309671c4dfe65ebd58281\SB_RAM40_4K. Using template $paramod$d1e07e07d74ca83c508e886c73cf8e7216ce4f9a\SB_RAM40_4K for cells of type $paramod$d1e07e07d74ca83c508e886c73cf8e7216ce4f9a\SB_RAM40_4K. Using template $paramod$0e9d59b0aa529313fb470eb883d3681c14cbd533\SB_RAM40_4K for cells of type $paramod$0e9d59b0aa529313fb470eb883d3681c14cbd533\SB_RAM40_4K. Using template $paramod$b2f76ebf376d4161fac9811f3d1d081eec373a8c\SB_RAM40_4K for cells of type $paramod$b2f76ebf376d4161fac9811f3d1d081eec373a8c\SB_RAM40_4K. Using template $paramod$c45611040bf4290b562e860e640d907d8fb59335\SB_RAM40_4K for cells of type $paramod$c45611040bf4290b562e860e640d907d8fb59335\SB_RAM40_4K. Using template $paramod$0be788f7e7503dc1ce265f93d57fe05b8fa23cd5\SB_RAM40_4K for cells of type $paramod$0be788f7e7503dc1ce265f93d57fe05b8fa23cd5\SB_RAM40_4K. Using template $paramod$b7274ee03d5bce333b8e1f04596dfacf63550bf2\SB_RAM40_4K for cells of type $paramod$b7274ee03d5bce333b8e1f04596dfacf63550bf2\SB_RAM40_4K. No more expansions possible. 2.42. Executing ICE40_WRAPCARRY pass (wrap carries). 2.43. Executing TECHMAP pass (map to technology primitives). 2.43.1. Executing Verilog-2005 frontend: /home/william/.local/bin/../share/yosys/ice40/ff_map.v Parsing Verilog input from `/home/william/.local/bin/../share/yosys/ice40/ff_map.v' to AST representation. Generating RTLIL representation for module `\$_DFF_N_'. Generating RTLIL representation for module `\$_DFF_P_'. Generating RTLIL representation for module `\$_DFFE_NP_'. Generating RTLIL representation for module `\$_DFFE_PP_'. Generating RTLIL representation for module `\$_DFF_NP0_'. Generating RTLIL representation for module `\$_DFF_NP1_'. Generating RTLIL representation for module `\$_DFF_PP0_'. Generating RTLIL representation for module `\$_DFF_PP1_'. Generating RTLIL representation for module `\$_DFFE_NP0P_'. Generating RTLIL representation for module `\$_DFFE_NP1P_'. Generating RTLIL representation for module `\$_DFFE_PP0P_'. Generating RTLIL representation for module `\$_DFFE_PP1P_'. Generating RTLIL representation for module `\$_SDFF_NP0_'. Generating RTLIL representation for module `\$_SDFF_NP1_'. Generating RTLIL representation for module `\$_SDFF_PP0_'. Generating RTLIL representation for module `\$_SDFF_PP1_'. Generating RTLIL representation for module `\$_SDFFCE_NP0P_'. Generating RTLIL representation for module `\$_SDFFCE_NP1P_'. Generating RTLIL representation for module `\$_SDFFCE_PP0P_'. Generating RTLIL representation for module `\$_SDFFCE_PP1P_'. Successfully finished Verilog frontend. 2.43.2. Continuing TECHMAP pass. No more expansions possible. Removed 220 unused cells and 19108 unused wires. 2.44. Executing OPT_LUT pass (optimize LUTs). Discovering LUTs. Number of LUTs: 1154 1-LUT 45 2-LUT 167 3-LUT 421 4-LUT 521 with \SB_CARRY (#0) 136 with \SB_CARRY (#1) 137 Eliminating LUTs. Number of LUTs: 1154 1-LUT 45 2-LUT 167 3-LUT 421 4-LUT 521 with \SB_CARRY (#0) 136 with \SB_CARRY (#1) 137 Combining LUTs. Number of LUTs: 1131 1-LUT 44 2-LUT 143 3-LUT 404 4-LUT 540 with \SB_CARRY (#0) 136 with \SB_CARRY (#1) 137 Eliminated 0 LUTs. Combined 23 LUTs. 2.45. Executing TECHMAP pass (map to technology primitives). 2.45.1. Executing Verilog-2005 frontend: /home/william/.local/bin/../share/yosys/ice40/cells_map.v Parsing Verilog input from `/home/william/.local/bin/../share/yosys/ice40/cells_map.v' to AST representation. Generating RTLIL representation for module `\$lut'. Successfully finished Verilog frontend. 2.45.2. Continuing TECHMAP pass. Using template $paramod$47a8214374025465e226fa66bee690ff33268a25\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0100 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00100000 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1000 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000001\LUT=2'01 for cells of type $lut. Using template $paramod$fd904e9e35cfd343a9df248824bd3f1408724879\$lut for cells of type $lut. Using template $paramod$608f40069c27841a5b3bdf03643a34bdc8974072\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000001 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10001010 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01000000 for cells of type $lut. Using template $paramod$d53578aacfd93124244778d88be0e90eb09c1b1b\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010000 for cells of type $lut. Using template $paramod$e3f15dbf386eb2d9773236c73b6cf924ec3294ee\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10000000 for cells of type $lut. Using template $paramod$fe9a0158d0352193457c4f5b6282ac86d35fb3ee\$lut for cells of type $lut. Using template $paramod$c1a19a87ccbbb03d43a72335db63f692ddf82cc1\$lut for cells of type $lut. Using template $paramod$6e238df02989b317f10820a22773676e71120644\$lut for cells of type $lut. Using template $paramod$658b9ed803f0d3d335616d3858b53e0a2522f1e8\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000010 for cells of type $lut. Using template $paramod$272652f6c6fbe9a75eff76e45cc7e2788835518b\$lut for cells of type $lut. Using template $paramod$7e8d331d1e06632d29fbdf6c3afc2de1856d3c67\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0001 for cells of type $lut. Using template $paramod$364c9ffbffac467d60dfec81bba4e18476c15602\$lut for cells of type $lut. Using template $paramod$873c285bdccf0ac2b60d2304ea5cd14bf211d2a6\$lut for cells of type $lut. Using template $paramod$a1d323730045824cfc84bb9f4ee8031f1c4dcc9e\$lut for cells of type $lut. Using template $paramod$5b4b4ed558983d9f3ab4c896a7a011d129b0db9a\$lut for cells of type $lut. Using template $paramod$15d5d7545b4e39a5d74b6d97cbeb7dc4faba912c\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10110000 for cells of type $lut. Using template $paramod$571404c0889eaf57f492cb5e37f8acb5df5852f9\$lut for cells of type $lut. Using template $paramod$59a754814ab3175aaf4b2bae6f26b235ecc61aa9\$lut for cells of type $lut. Using template $paramod$91d6743ceb0f093b57d242b538f7f23d2346d4c9\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0010 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001000 for cells of type $lut. Using template $paramod$d9c3d189aabf20520d672302e8d5bb485224c507\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01000010 for cells of type $lut. Using template $paramod$4cab3b31c601551ff65536bf4f533afa0b2094ee\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101001 for cells of type $lut. Using template $paramod$fdcae86fcfd036c1880a04306ae771a9d7579c31\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01110010 for cells of type $lut. Using template $paramod$0d3ac82cf5b8a192d5ff4c23e3143360366ae882\$lut for cells of type $lut. Using template $paramod$8e44661def013b6bf9fe6f8b049ef2c838d749f9\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00110001 for cells of type $lut. Using template $paramod$bb4a03ba87e7a3077b7fcb86d509b6e1445f0bbf\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1110 for cells of type $lut. Using template $paramod$9c65fdfac74256c2eb67dd209b598e25d1f0a099\$lut for cells of type $lut. Using template $paramod$59f2a3e232df3029c8bc36978b9bbe72a71dfb5a\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100100 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100010 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01000111 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101000 for cells of type $lut. Using template $paramod$368ece0cbe0dd8813956f5c0ea41432c34a980c2\$lut for cells of type $lut. Using template $paramod$3357e04690749b6c89de0fcd28f53cd216bd2047\$lut for cells of type $lut. Using template $paramod$3d98cbd933baee327b5d76a0c6e6cddc5563d2bd\$lut for cells of type $lut. Using template $paramod$daac9b1e7bb2ac018f7132a3fbe0026ddd7b1a71\$lut for cells of type $lut. Using template $paramod$6b0849254d6c87461fb93e37cc18f089f61eb912\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11011111 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10111000 for cells of type $lut. Using template $paramod$c227f721a44fefdada39f6c9acbbd79680d6e12a\$lut for cells of type $lut. Using template $paramod$a36debbcfde9e32a01ea5076ccf3d75225452c4d\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000100 for cells of type $lut. Using template $paramod$f8f63b209b7230e81958663ff24fef1613156af7\$lut for cells of type $lut. Using template $paramod$cd05f04889088c47a0a5abae8c2d644fd314805e\$lut for cells of type $lut. Using template $paramod$153c6cdaaddbc43e6ef3facd06aa851de33910ae\$lut for cells of type $lut. Using template $paramod$e01a027fedb28671a20c130493a89c7afd4e87d3\$lut for cells of type $lut. Using template $paramod$4ddc2ad0019e4b996b49a3372d822a4601fc4ba8\$lut for cells of type $lut. Using template $paramod$ab8bb87959c5d7cfa27886cee1355b38e054a61a\$lut for cells of type $lut. Using template $paramod$82b4a585d1edcb5c6e755dc9bd3392228a1c1304\$lut for cells of type $lut. Using template $paramod$fda6887b37f599177ed9cb69271d882b63df7e66\$lut for cells of type $lut. Using template $paramod$f9813472aa48e533b3838c6f2316dc2e78c66111\$lut for cells of type $lut. Using template $paramod$769bdbbde83614df0f4ab5f54e777ded51bb10ce\$lut for cells of type $lut. Using template $paramod$ea0faad69a26c91786a25961ea149d0e0961eb1f\$lut for cells of type $lut. Using template $paramod$7ffc04c088a4897014506d1e561a14b627924059\$lut for cells of type $lut. Using template $paramod$06e62c2045624c211a1abe4f2f36c8f22c688165\$lut for cells of type $lut. Using template $paramod$32ccf65669c41e1e3bce1f16051f6d60ad96a2a0\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000111 for cells of type $lut. Using template $paramod$b2e8d279775d333b39e310bd45fd5952acdde290\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00101110 for cells of type $lut. Using template $paramod$54b31a4ca2fcdd8a84ca32ff455a989423627fef\$lut for cells of type $lut. Using template $paramod$c5479cb3b02237832e868d4808b3a7f1be08f618\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10001101 for cells of type $lut. Using template $paramod$c2ec04e79a837992e22a44516a441e33767962c2\$lut for cells of type $lut. Using template $paramod$8d7a8d6e3356de09670738ba85f2c6b874f6b06d\$lut for cells of type $lut. Using template $paramod$c63fb63be97a9db4ce7bd031e26652a8b349a094\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111101 for cells of type $lut. Using template $paramod$b888b70a5f7e5362c3d8df906c5f324feaeffd36\$lut for cells of type $lut. Using template $paramod$edde25994980e1eecfe31ae777b35d7142a4d423\$lut for cells of type $lut. Using template $paramod$034a69dd110db95ee917f313eafd6833fc6595f9\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10111111 for cells of type $lut. Using template $paramod$8be603794459732f9a374f76041b510fc63b115b\$lut for cells of type $lut. Using template $paramod$6deead41a97e885fdfb7651ed7486bc07c319d2a\$lut for cells of type $lut. Using template $paramod$9ea238b3c4036add2bd96e5aaac8768e1ad77c5a\$lut for cells of type $lut. Using template $paramod$101238f3d8d49ab12a9b49a2f01cd503b26e9c61\$lut for cells of type $lut. Using template $paramod$30305e55a780880b9c824fe3509a4d981acb0f2b\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0111 for cells of type $lut. Using template $paramod$7b8680941227e98df3d68b586700721655a86671\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11010000 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1011 for cells of type $lut. Using template $paramod$d76df6204e5e08a70e04785415e78377888545e3\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001010 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01001110 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10110001 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11011000 for cells of type $lut. Using template $paramod$e4b832d686d12318ec0715f027fe549b42e45c20\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01011100 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101100 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1101 for cells of type $lut. Using template $paramod$12d55b60f0f4993cdeef74f2f65f385722841c5f\$lut for cells of type $lut. Using template $paramod$15deee21bfb7f6f9f3963bae01e1abc87728ceb1\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100000 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001000 for cells of type $lut. Using template $paramod$baa9d2fb2d21010939721b85aa9f11effe0b53c4\$lut for cells of type $lut. Using template $paramod$a7c07944e10969b2e1fd563a5b72f89493cb3705\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11101111 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11000111 for cells of type $lut. Using template $paramod$c8f16510db975553c8b0be1064e8f5234175f8a8\$lut for cells of type $lut. Using template $paramod$a4640096cbef09c4ef8613155a589c40164ac034\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01101010 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10010101 for cells of type $lut. Using template $paramod$e6d61e5e52018f8d3fe280aad543cad1e662fe83\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01110000 for cells of type $lut. Using template $paramod$d5c7dda3e544463bf43ed73dadb51262f5dcf2fe\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010011 for cells of type $lut. Using template $paramod$3548f6e93628807ae6cc989ec88fe8ae640cb47a\$lut for cells of type $lut. Using template $paramod$ec6c71d259df49ae0842190ffaff1179e43a8db4\$lut for cells of type $lut. Using template $paramod$95405290ab850162780aaf9d904598a9a9ee1d4b\$lut for cells of type $lut. Using template $paramod$62e34d236b5cf9e50e7481784c0097067a15fba4\$lut for cells of type $lut. Using template $paramod$09deb89cf77b6e37f6ed7fef8d797dc05c0b2eee\$lut for cells of type $lut. Using template $paramod$66f4e42f6ecc06064dc14df2d3ed673c4ae6d667\$lut for cells of type $lut. Using template $paramod$bf80ab5b82bc1c590371914612ed4ab80a2743a3\$lut for cells of type $lut. Using template $paramod$f85f1073c412d406200a6a72283f918c8b751314\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11000100 for cells of type $lut. Using template $paramod$963966c07502ed1cd96da8997c92d05fa056bcad\$lut for cells of type $lut. Using template $paramod$ea79e410ad0f4fc3326666c891e1f3992816d636\$lut for cells of type $lut. Using template $paramod$a8b2b0f3a3fd7b01c99e8d61bb72f602bd41af54\$lut for cells of type $lut. Using template $paramod$70dcc34b3190ff5541006bab0f38ffad9d439d5a\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00100011 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11010101 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001011 for cells of type $lut. Using template $paramod$78107355136c565d78c8ffe30e4a20f55dedc5b7\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01011101 for cells of type $lut. Using template $paramod$7793af14a1d1a9df09b7264353e3dfaa774cd044\$lut for cells of type $lut. Using template $paramod$cd05caaf261e4148f336c0ecc488c806e4433d99\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10001100 for cells of type $lut. Using template $paramod$3e63470ea7a06b3eefdfb990254dd83d20fa13a7\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01110101 for cells of type $lut. Using template $paramod$12879138d1e376f344e47ea40be66b776233be75\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01001111 for cells of type $lut. Using template $paramod$31114d87be01f977936de4d238d2be8c5bca7194\$lut for cells of type $lut. Using template $paramod$0cdbe1f01535765535b23b1673f9cb35dee803e5\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10001111 for cells of type $lut. Using template $paramod$b199427913ecba49d7426ad376614113d06b8e17\$lut for cells of type $lut. Using template $paramod$728e616c918eb05878d70b2bb240e381ea2847b9\$lut for cells of type $lut. Using template $paramod$325e90edf97670f9dea57833ae1f51a5e8bcddea\$lut for cells of type $lut. Using template $paramod$d0cfbfa794431f7e2ccafbbeaaefbd5ed7deeac7\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00111011 for cells of type $lut. Using template $paramod$f28aede8a07a53ff316cc6f8627c7d8a2337a88a\$lut for cells of type $lut. Using template $paramod$9dd298ae76fb41ac94779a83c068607fbc09ce4f\$lut for cells of type $lut. Using template $paramod$b4d0f4738a5ce50c7f36c2aa2ecc09cfb874f2b6\$lut for cells of type $lut. Using template $paramod$65fb1d96ed353a5487bb4df51139b6105a246601\$lut for cells of type $lut. Using template $paramod$4e79aa6839e287ee36e65fa83c13a532a028e9cd\$lut for cells of type $lut. Using template $paramod$11ec7271d8e6e5aeaace08c13e4c601f10e31038\$lut for cells of type $lut. Using template $paramod$833582361e14b3ee2e66ad676022ab35d7aa7e28\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00011011 for cells of type $lut. Using template $paramod$66caeb00a39d236782a97659e3bd99621b74681b\$lut for cells of type $lut. Using template $paramod$f5c23b297b0a8ca096118d63d2c74ddd6cbea134\$lut for cells of type $lut. Using template $paramod$8cac5452d526045503c5864c3a1dac0121c7053e\$lut for cells of type $lut. Using template $paramod$de5328836923c44c99600bcab852423201246f91\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11110111 for cells of type $lut. Using template $paramod$825b59cbfb58847dd28f50a3872d124190d3eb19\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11110100 for cells of type $lut. Using template $paramod$9a20e5eb914da7530de8ea5af782be66b9acb237\$lut for cells of type $lut. Using template $paramod$98da953dac84989c1dec711ba4d909885d65c4dd\$lut for cells of type $lut. Using template $paramod$08dcfd45ddad93da5ec819a79edef2ff5d3a63f5\$lut for cells of type $lut. Using template $paramod$1b4dd6457d07f8f165ec99061b8d6c5023635c5b\$lut for cells of type $lut. Using template $paramod$d6ca727e39f31d51d29072e0f33aa09c65e37336\$lut for cells of type $lut. Using template $paramod$4385b611926e5c0509dba4de58311d325da0ff0d\$lut for cells of type $lut. Using template $paramod$da2f95476331ffa2143f8212db8aff730de806a0\$lut for cells of type $lut. Using template $paramod$4a433f3233d3530f1cdf441edd4d4bf4cc5f439e\$lut for cells of type $lut. Using template $paramod$4fd3428c4b8b1accf8f8fb4bb88555a2b5fa688d\$lut for cells of type $lut. Using template $paramod$e49f6e3576ef1a6d2f58c54414dbb786af8cc869\$lut for cells of type $lut. Using template $paramod$71d951b20e73043168c1656217d126e617052faa\$lut for cells of type $lut. Using template $paramod$afb8959a93937986ded51b1cddcab9e31c6ea2ed\$lut for cells of type $lut. Using template $paramod$097592bb16245531f0716c5ddb18d7090f9c7d9d\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00101111 for cells of type $lut. Using template $paramod$cdfb4ce36e9b97ab980954e4bd7262833a7086a8\$lut for cells of type $lut. Using template $paramod$dd7c1583fe0ade167c7826c594e5d16b758a72fe\$lut for cells of type $lut. Using template $paramod$0de052767abdccc3aefc818722bdc3c7850d25d6\$lut for cells of type $lut. Using template $paramod$9850450c7f2ce6ec6d61697515f47872a7c4eee5\$lut for cells of type $lut. Using template $paramod$a5fa16f6792f721e525cbdcedb4e5d3e91843765\$lut for cells of type $lut. Using template $paramod$ab2e45f7a350a5d7d54d88d8019d5256ae32568f\$lut for cells of type $lut. Using template $paramod$9ce83c401f07863ef6c07aa36141bf86d010bac8\$lut for cells of type $lut. Using template $paramod$5766b753e513aa2393ffc25ef94ebc79dc098484\$lut for cells of type $lut. Using template $paramod$ff10621ff350133ce54c2c9c3516ef034e8cfe58\$lut for cells of type $lut. Using template $paramod$c24ed72ebb67e9ead6029e42e909ef7fc0abbb11\$lut for cells of type $lut. Using template $paramod$3702268f692b8bf258e428f65d3bca4e1f76d98b\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00100001 for cells of type $lut. Using template $paramod$a50bbaf70b48eb6d78317eddf4f7e11e8988acec\$lut for cells of type $lut. Using template $paramod$6d6beead1425af15cf78b27fd9b11b41b5d4bce8\$lut for cells of type $lut. Using template $paramod$a5516fc31d1e552de2435200bb732b4d4ad63a9c\$lut for cells of type $lut. Using template $paramod$25003f26a78bb2f583f23824f1e0b8cc16b88761\$lut for cells of type $lut. Using template $paramod$29e6d4598488760861f6b73d2b7f65cb302fdcde\$lut for cells of type $lut. Using template $paramod$609ff53b8e25fddda2f58be8d19c2d47b81baf45\$lut for cells of type $lut. Using template $paramod$f840a6057f1d372c3e6a8a9fa5382749feb221f5\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10100011 for cells of type $lut. Using template $paramod$734cd1512f671d92bc4f41153da0d9781801dd98\$lut for cells of type $lut. Using template $paramod$94ac66a11090dca84889e55fcf03297912a5b7ec\$lut for cells of type $lut. Using template $paramod$5a2475f0ff8adfa6c48e46c1977dad3962daa33d\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10100010 for cells of type $lut. Using template $paramod$39a3022e55aa03d0b5478da3a6d9fcb662c62e56\$lut for cells of type $lut. No more expansions possible. Removed 0 unused cells and 2568 unused wires. 2.46. Executing AUTONAME pass. Renamed 29180 objects in module top (68 iterations). 2.47. Executing HIERARCHY pass (managing design hierarchy). 2.47.1. Analyzing design hierarchy.. Top module: \top 2.47.2. Analyzing design hierarchy.. Top module: \top Removed 0 unused modules. 2.48. Printing statistics. === top === Number of wires: 1402 Number of wire bits: 7955 Number of public wires: 1402 Number of public wire bits: 7955 Number of memories: 0 Number of memory bits: 0 Number of processes: 0 Number of cells: 1719 SB_CARRY 138 SB_DFF 1 SB_DFFE 44 SB_DFFESR 290 SB_DFFSR 84 SB_GB_IO 1 SB_IO 16 SB_LUT4 1131 SB_RAM40_4K 14 2.49. Executing CHECK pass (checking for obvious problems). Checking module top... Found and reported 0 problems. 3. Executing JSON backend. End of script. Logfile hash: 9c76fe9dd2, CPU: user 9.76s system 0.04s, MEM: 69.23 MB peak Yosys 0.35+39 (git sha1 031ad38b5, sccache gcc 9.4.0-1ubuntu1~20.04.2 -fPIC -Os) Time spent: 46% 11x techmap (5 sec), 11% 1x abc9_exe (1 sec), ...