::FROM-WRITER; // designname: osch // Creation time stamp: 02/08/23 15:55:38 design osch { device { architecture xo2c00; device LCMXO2-1200HC; package QFN32; performance "6"; } // Writing 6 properties. property { LSE_CPS_MAP_FILE string "xxx_lse_sign_file"; "PINNAME:0" string "clk"; "PINNAME:1" string "stdby"; "PINTYPE:0" string "IN"; "PINTYPE:1" string "OUT"; "SIGNAME:PUR" string "VCC_net"; } // End of property list. // The Design macro definitions. // The Design macro instances. // The Design Comps. comp stdby { // Writing 3 properties. property { "#%PAD%PINID" long 1; LSE_CPS_ID_1 string "IOBUF"; NGID0 long 1; } // End of property list. logical { cellmodel-name PIO; program "TRIMUX:PADDT:::PADDT=0 " "IOBUF:::PULLMODE=DOWN,DRIVE=8, \" "SLEWRATE=SLOW,HYSTERESIS=NA " "DATAMUX:PADDO " "VREF:OFF " "ODMUX:TRIMUX " "LVDSMUX:DATAMUX "; primitive IOBUF stdby_pad; primitive PAD stdby; } site "11"; } comp clk { // Writing 3 properties. property { "#%PAD%PINID" long 0; LSE_CPS_ID_2 string "IOBUF"; NGID0 long 3; } // End of property list. logical { cellmodel-name PIO; program "PADDI:PADDI " "IOBUF:::PULLMODE=DOWN,CLAMP=ON " "VREF:OFF " "PGMUX:INBUF " "INRDMUX:PGMUX "; primitive IOBUF stdby_c_pad; primitive PAD clk; } site "13"; } // The Design Signals. signal stdby_c_c { signal-pins // drivers (clk, PADDI), // loads (stdby, PADDO); route R11C9_V00B0200.R11C9_JA0, R11C10_H02W0001.R11C9_V00B0200, R11C11_JQ0.R11C10_H02W0001, R12C11_JDIA.R11C11_JQ0, R11C9_JA0.R12C9_JPADDOA, R12C9_JPADDOA.R12C9_PADDOA_PIO, R12C11_JPADDIA_PIO.R12C11_JDIA; } }