// ----------------------------------------------------------------------------- // Auto-Generated by: __ _ __ _ __ // / / (_) /____ | |/_/ // / /__/ / __/ -_)> < // /____/_/\__/\__/_/|_| // Build your hardware, easily! // https://github.com/enjoy-digital/litex // // Filename : top.v // Device : Unknown // LiteX sha1 : 0bd2abf6 // Date : 2022-04-06 03:56:31 //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // Module //------------------------------------------------------------------------------ module top ( input wire sink_valid, output wire sink_ready, input wire sink_first, input wire sink_last, input wire [7:0] sink_payload_data, output wire source_valid, input wire source_ready, output wire source_first, output wire source_last, output wire [7:0] source_payload_data ); //------------------------------------------------------------------------------ // Signals //------------------------------------------------------------------------------ reg rxtx_re = 1'd0; reg [7:0] rxtx_r = 8'd0; reg rxtx_we = 1'd0; wire [7:0] rxtx_w; wire txfull_status; wire rxempty_status; wire irq; wire tx_status; reg tx_pending = 1'd0; wire tx_trigger; reg tx_clear = 1'd0; reg tx_trigger_d = 1'd0; wire rx_status; reg rx_pending = 1'd0; wire rx_trigger; reg rx_clear = 1'd0; reg rx_trigger_d = 1'd0; wire eventmanager_tx0; wire eventmanager_rx0; wire eventmanager_tx1; wire eventmanager_rx1; reg [1:0] eventmanager_status = 2'd0; reg eventmanager_re = 1'd0; reg [1:0] eventmanager_r = 2'd0; reg [1:0] eventmanager_storage = 2'd0; wire txempty_status; wire rxfull_status; wire tx_fifo_sink_valid; wire tx_fifo_sink_ready; reg tx_fifo_sink_first = 1'd0; reg tx_fifo_sink_last = 1'd0; wire [7:0] tx_fifo_sink_payload_data; wire tx_fifo_source_valid; wire tx_fifo_source_ready; wire tx_fifo_source_first; wire tx_fifo_source_last; wire [7:0] tx_fifo_source_payload_data; wire tx_fifo_re; reg tx_fifo_readable = 1'd0; wire tx_fifo_syncfifo_we; wire tx_fifo_syncfifo_writable; wire tx_fifo_syncfifo_re; wire tx_fifo_syncfifo_readable; wire [9:0] tx_fifo_syncfifo_din; wire [9:0] tx_fifo_syncfifo_dout; reg [4:0] tx_fifo_level0 = 5'd0; reg tx_fifo_replace = 1'd0; reg [3:0] tx_fifo_produce = 4'd0; reg [3:0] tx_fifo_consume = 4'd0; reg [3:0] tx_fifo_wrport_adr = 4'd0; wire [9:0] tx_fifo_wrport_dat_r; wire tx_fifo_wrport_we; wire [9:0] tx_fifo_wrport_dat_w; wire tx_fifo_do_read; wire [3:0] tx_fifo_rdport_adr; wire [9:0] tx_fifo_rdport_dat_r; wire tx_fifo_rdport_re; wire [4:0] tx_fifo_level1; wire [7:0] tx_fifo_fifo_in_payload_data; wire tx_fifo_fifo_in_first; wire tx_fifo_fifo_in_last; wire [7:0] tx_fifo_fifo_out_payload_data; wire tx_fifo_fifo_out_first; wire tx_fifo_fifo_out_last; wire rx_fifo_sink_valid; wire rx_fifo_sink_ready; wire rx_fifo_sink_first; wire rx_fifo_sink_last; wire [7:0] rx_fifo_sink_payload_data; wire rx_fifo_source_valid; wire rx_fifo_source_ready; wire rx_fifo_source_first; wire rx_fifo_source_last; wire [7:0] rx_fifo_source_payload_data; wire rx_fifo_re; reg rx_fifo_readable = 1'd0; wire rx_fifo_syncfifo_we; wire rx_fifo_syncfifo_writable; wire rx_fifo_syncfifo_re; wire rx_fifo_syncfifo_readable; wire [9:0] rx_fifo_syncfifo_din; wire [9:0] rx_fifo_syncfifo_dout; reg [4:0] rx_fifo_level0 = 5'd0; reg rx_fifo_replace = 1'd0; reg [3:0] rx_fifo_produce = 4'd0; reg [3:0] rx_fifo_consume = 4'd0; reg [3:0] rx_fifo_wrport_adr = 4'd0; wire [9:0] rx_fifo_wrport_dat_r; wire rx_fifo_wrport_we; wire [9:0] rx_fifo_wrport_dat_w; wire rx_fifo_do_read; wire [3:0] rx_fifo_rdport_adr; wire [9:0] rx_fifo_rdport_dat_r; wire rx_fifo_rdport_re; wire [4:0] rx_fifo_level1; wire [7:0] rx_fifo_fifo_in_payload_data; wire rx_fifo_fifo_in_first; wire rx_fifo_fifo_in_last; wire [7:0] rx_fifo_fifo_out_payload_data; wire rx_fifo_fifo_out_first; wire rx_fifo_fifo_out_last; reg sys_clk = 1'd0; reg sys_rst = 1'd0; //------------------------------------------------------------------------------ // Combinatorial Logic //------------------------------------------------------------------------------ assign tx_fifo_sink_valid = rxtx_re; assign tx_fifo_sink_payload_data = rxtx_r; assign source_valid = tx_fifo_source_valid; assign tx_fifo_source_ready = source_ready; assign source_first = tx_fifo_source_first; assign source_last = tx_fifo_source_last; assign source_payload_data = tx_fifo_source_payload_data; assign txfull_status = (~tx_fifo_sink_ready); assign txempty_status = (~tx_fifo_source_valid); assign tx_trigger = tx_fifo_sink_ready; assign rx_fifo_sink_valid = sink_valid; assign sink_ready = rx_fifo_sink_ready; assign rx_fifo_sink_first = sink_first; assign rx_fifo_sink_last = sink_last; assign rx_fifo_sink_payload_data = sink_payload_data; assign rxtx_w = rx_fifo_source_payload_data; assign rx_fifo_source_ready = (rx_clear | (1'd0 & rxtx_we)); assign rxempty_status = (~rx_fifo_source_valid); assign rxfull_status = (~rx_fifo_sink_ready); assign rx_trigger = rx_fifo_source_valid; assign eventmanager_tx0 = tx_status; assign eventmanager_tx1 = tx_pending; always @(*) begin tx_clear <= 1'd0; if ((eventmanager_re & eventmanager_r[0])) begin tx_clear <= 1'd1; end end assign eventmanager_rx0 = rx_status; assign eventmanager_rx1 = rx_pending; always @(*) begin rx_clear <= 1'd0; if ((eventmanager_re & eventmanager_r[1])) begin rx_clear <= 1'd1; end end assign irq = ((eventmanager_status[0] & eventmanager_storage[0]) | (eventmanager_status[1] & eventmanager_storage[1])); assign tx_status = tx_trigger; assign rx_status = rx_trigger; assign tx_fifo_syncfifo_din = {tx_fifo_fifo_in_last, tx_fifo_fifo_in_first, tx_fifo_fifo_in_payload_data}; assign {tx_fifo_fifo_out_last, tx_fifo_fifo_out_first, tx_fifo_fifo_out_payload_data} = tx_fifo_syncfifo_dout; assign tx_fifo_sink_ready = tx_fifo_syncfifo_writable; assign tx_fifo_syncfifo_we = tx_fifo_sink_valid; assign tx_fifo_fifo_in_first = tx_fifo_sink_first; assign tx_fifo_fifo_in_last = tx_fifo_sink_last; assign tx_fifo_fifo_in_payload_data = tx_fifo_sink_payload_data; assign tx_fifo_source_valid = tx_fifo_readable; assign tx_fifo_source_first = tx_fifo_fifo_out_first; assign tx_fifo_source_last = tx_fifo_fifo_out_last; assign tx_fifo_source_payload_data = tx_fifo_fifo_out_payload_data; assign tx_fifo_re = tx_fifo_source_ready; assign tx_fifo_syncfifo_re = (tx_fifo_syncfifo_readable & ((~tx_fifo_readable) | tx_fifo_re)); assign tx_fifo_level1 = (tx_fifo_level0 + tx_fifo_readable); always @(*) begin tx_fifo_wrport_adr <= 4'd0; if (tx_fifo_replace) begin tx_fifo_wrport_adr <= (tx_fifo_produce - 1'd1); end else begin tx_fifo_wrport_adr <= tx_fifo_produce; end end assign tx_fifo_wrport_dat_w = tx_fifo_syncfifo_din; assign tx_fifo_wrport_we = (tx_fifo_syncfifo_we & (tx_fifo_syncfifo_writable | tx_fifo_replace)); assign tx_fifo_do_read = (tx_fifo_syncfifo_readable & tx_fifo_syncfifo_re); assign tx_fifo_rdport_adr = tx_fifo_consume; assign tx_fifo_syncfifo_dout = tx_fifo_rdport_dat_r; assign tx_fifo_rdport_re = tx_fifo_do_read; assign tx_fifo_syncfifo_writable = (tx_fifo_level0 != 5'd16); assign tx_fifo_syncfifo_readable = (tx_fifo_level0 != 1'd0); assign rx_fifo_syncfifo_din = {rx_fifo_fifo_in_last, rx_fifo_fifo_in_first, rx_fifo_fifo_in_payload_data}; assign {rx_fifo_fifo_out_last, rx_fifo_fifo_out_first, rx_fifo_fifo_out_payload_data} = rx_fifo_syncfifo_dout; assign rx_fifo_sink_ready = rx_fifo_syncfifo_writable; assign rx_fifo_syncfifo_we = rx_fifo_sink_valid; assign rx_fifo_fifo_in_first = rx_fifo_sink_first; assign rx_fifo_fifo_in_last = rx_fifo_sink_last; assign rx_fifo_fifo_in_payload_data = rx_fifo_sink_payload_data; assign rx_fifo_source_valid = rx_fifo_readable; assign rx_fifo_source_first = rx_fifo_fifo_out_first; assign rx_fifo_source_last = rx_fifo_fifo_out_last; assign rx_fifo_source_payload_data = rx_fifo_fifo_out_payload_data; assign rx_fifo_re = rx_fifo_source_ready; assign rx_fifo_syncfifo_re = (rx_fifo_syncfifo_readable & ((~rx_fifo_readable) | rx_fifo_re)); assign rx_fifo_level1 = (rx_fifo_level0 + rx_fifo_readable); always @(*) begin rx_fifo_wrport_adr <= 4'd0; if (rx_fifo_replace) begin rx_fifo_wrport_adr <= (rx_fifo_produce - 1'd1); end else begin rx_fifo_wrport_adr <= rx_fifo_produce; end end assign rx_fifo_wrport_dat_w = rx_fifo_syncfifo_din; assign rx_fifo_wrport_we = (rx_fifo_syncfifo_we & (rx_fifo_syncfifo_writable | rx_fifo_replace)); assign rx_fifo_do_read = (rx_fifo_syncfifo_readable & rx_fifo_syncfifo_re); assign rx_fifo_rdport_adr = rx_fifo_consume; assign rx_fifo_syncfifo_dout = rx_fifo_rdport_dat_r; assign rx_fifo_rdport_re = rx_fifo_do_read; assign rx_fifo_syncfifo_writable = (rx_fifo_level0 != 5'd16); assign rx_fifo_syncfifo_readable = (rx_fifo_level0 != 1'd0); //------------------------------------------------------------------------------ // Synchronous Logic //------------------------------------------------------------------------------ always @(posedge sys_clk) begin if (tx_clear) begin tx_pending <= 1'd0; end tx_trigger_d <= tx_trigger; if ((tx_trigger & (~tx_trigger_d))) begin tx_pending <= 1'd1; end if (rx_clear) begin rx_pending <= 1'd0; end rx_trigger_d <= rx_trigger; if ((rx_trigger & (~rx_trigger_d))) begin rx_pending <= 1'd1; end if (tx_fifo_syncfifo_re) begin tx_fifo_readable <= 1'd1; end else begin if (tx_fifo_re) begin tx_fifo_readable <= 1'd0; end end if (((tx_fifo_syncfifo_we & tx_fifo_syncfifo_writable) & (~tx_fifo_replace))) begin tx_fifo_produce <= (tx_fifo_produce + 1'd1); end if (tx_fifo_do_read) begin tx_fifo_consume <= (tx_fifo_consume + 1'd1); end if (((tx_fifo_syncfifo_we & tx_fifo_syncfifo_writable) & (~tx_fifo_replace))) begin if ((~tx_fifo_do_read)) begin tx_fifo_level0 <= (tx_fifo_level0 + 1'd1); end end else begin if (tx_fifo_do_read) begin tx_fifo_level0 <= (tx_fifo_level0 - 1'd1); end end if (rx_fifo_syncfifo_re) begin rx_fifo_readable <= 1'd1; end else begin if (rx_fifo_re) begin rx_fifo_readable <= 1'd0; end end if (((rx_fifo_syncfifo_we & rx_fifo_syncfifo_writable) & (~rx_fifo_replace))) begin rx_fifo_produce <= (rx_fifo_produce + 1'd1); end if (rx_fifo_do_read) begin rx_fifo_consume <= (rx_fifo_consume + 1'd1); end if (((rx_fifo_syncfifo_we & rx_fifo_syncfifo_writable) & (~rx_fifo_replace))) begin if ((~rx_fifo_do_read)) begin rx_fifo_level0 <= (rx_fifo_level0 + 1'd1); end end else begin if (rx_fifo_do_read) begin rx_fifo_level0 <= (rx_fifo_level0 - 1'd1); end end if (sys_rst) begin tx_pending <= 1'd0; tx_trigger_d <= 1'd0; rx_pending <= 1'd0; rx_trigger_d <= 1'd0; tx_fifo_readable <= 1'd0; tx_fifo_level0 <= 5'd0; tx_fifo_produce <= 4'd0; tx_fifo_consume <= 4'd0; rx_fifo_readable <= 1'd0; rx_fifo_level0 <= 5'd0; rx_fifo_produce <= 4'd0; rx_fifo_consume <= 4'd0; end end //------------------------------------------------------------------------------ // Specialized Logic //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // Memory storage: 16-words x 10-bit //------------------------------------------------------------------------------ // Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 10 // Port 1 | Read: Sync | Write: ---- | reg [9:0] storage[0:15]; reg [9:0] storage_dat0; reg [9:0] storage_dat1; always @(posedge sys_clk) begin if (tx_fifo_wrport_we) storage[tx_fifo_wrport_adr] <= tx_fifo_wrport_dat_w; storage_dat0 <= storage[tx_fifo_wrport_adr]; end always @(posedge sys_clk) begin if (tx_fifo_rdport_re) storage_dat1 <= storage[tx_fifo_rdport_adr]; end assign tx_fifo_wrport_dat_r = storage_dat0; assign tx_fifo_rdport_dat_r = storage_dat1; //------------------------------------------------------------------------------ // Memory storage_1: 16-words x 10-bit //------------------------------------------------------------------------------ // Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 10 // Port 1 | Read: Sync | Write: ---- | reg [9:0] storage_1[0:15]; reg [9:0] storage_1_dat0; reg [9:0] storage_1_dat1; always @(posedge sys_clk) begin if (rx_fifo_wrport_we) storage_1[rx_fifo_wrport_adr] <= rx_fifo_wrport_dat_w; storage_1_dat0 <= storage_1[rx_fifo_wrport_adr]; end always @(posedge sys_clk) begin if (rx_fifo_rdport_re) storage_1_dat1 <= storage_1[rx_fifo_rdport_adr]; end assign rx_fifo_wrport_dat_r = storage_1_dat0; assign rx_fifo_rdport_dat_r = storage_1_dat1; endmodule // ----------------------------------------------------------------------------- // Auto-Generated by LiteX on 2022-04-06 03:56:31. //------------------------------------------------------------------------------