from amaranth import *
from amaranth.sim import Simulator
from amaranth.back import rtlil, verilog
import amaranth_playground


en = Signal()
count = Signal(4)
m = Module()
# m.domains += ClockDomain("clk1"), ClockDomain("clk2")


async def testbench(ctx):
    next_val = 1

    for _ in range(20):
        await ctx.delay(20e-6)
        ctx.set(count, 1)

        if next_val == 0:
            next_val = 1
        else:
            next_val = 0



sim = Simulator(m)
sim.add_testbench(testbench)
with amaranth_playground.show_waveforms(sim):
    sim.run()

# amaranth_playground.show_verilog(verilog.convert(m, ports=[count]))
# amaranth_playground.show_rtlil(rtlil.convert(m, ports=[count]))