diff --git a/src/sentinel/top.py b/src/sentinel/top.py
index 9d091ba..092d6c1 100644
--- a/src/sentinel/top.py
+++ b/src/sentinel/top.py
@@ -2,7 +2,13 @@
 
 from amaranth import Signal, Module
 from amaranth.lib.wiring import Component, Signature, Out, In, connect, flipped
-from amaranth_soc import wishbone
+from importlib.util import find_spec
+
+try:
+    from amaranth_soc import wishbone
+except ImportError:
+    pass
+
 
 from .alu import ALU, ASrcMux, BSrcMux
 from .align import AddressAlign, WriteDataAlign
@@ -205,9 +211,24 @@ class Top(Component):
         self.exception_router = ExceptionRouter()
         self.wdata_align = WriteDataAlign()
 
+        if find_spec("amaranth_soc"):
+            bus_sig = wishbone.Signature(addr_width=30, data_width=32, granularity=8) # pyright: ignore[reportPossiblyUnboundVariable]
+        else:
+            bus_sig = Signature(
+                {
+                    "adr":   Out(self.addr_width),
+                    "dat_w": Out(self.data_width),
+                    "dat_r": In(self.data_width),
+                    "sel":   Out(self.data_width // self.granularity),
+                    "cyc":   Out(1),
+                    "stb":   Out(1),
+                    "we":    Out(1),
+                    "ack":   In(1),
+                }
+            )
+
         sig = {
-                "bus": Out(wishbone.Signature(addr_width=30, data_width=32,
-                                              granularity=8)),
+                "bus": Out(bus_sig),
                 "irq": In(1)
         }
         if self.formal: