William@DESKTOP-H0PMN4M MINGW64 /c/msys64/home/William/Projects/FPGA/litex/SoCs/orangecrab-feather
$ python -m orangecrab_feather --build --load --ecppack-compress
INFO:SoC:        __   _ __      _  __
INFO:SoC:       / /  (_) /____ | |/_/
INFO:SoC:      / /__/ / __/ -_)>  <
INFO:SoC:     /____/_/\__/\__/_/|_|
INFO:SoC:  Build your hardware, easily!
INFO:SoC:-------------------------------------------------------------------------------- INFO:SoC:Creating SoC... (2022-03-19 23:43:38)
INFO:SoC:-------------------------------------------------------------------------------- INFO:SoC:FPGA device : LFE5U-25F-8MG285C.
INFO:SoC:System clock: 48.000MHz.
INFO:SoCBusHandler:Creating Bus Handler...
INFO:SoCBusHandler:32-bit wishbone Bus, 4.0GiB Address Space.
INFO:SoCBusHandler:Adding reserved Bus Regions...
INFO:SoCBusHandler:Bus Handler created.
INFO:SoCCSRHandler:Creating CSR Handler...
INFO:SoCCSRHandler:32-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging, big Ordering (Up to 32 Locations).
INFO:SoCCSRHandler:Adding reserved CSRs...
INFO:SoCCSRHandler:CSR Handler created.
INFO:SoCIRQHandler:Creating IRQ Handler...
INFO:SoCIRQHandler:IRQ Handler (up to 32 Locations).
INFO:SoCIRQHandler:Adding reserved IRQs...
INFO:SoCIRQHandler:IRQ Handler created.
INFO:SoC:-------------------------------------------------------------------------------- INFO:SoC:Initial SoC:
INFO:SoC:-------------------------------------------------------------------------------- INFO:SoC:32-bit wishbone Bus, 4.0GiB Address Space.
INFO:SoC:32-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging, big Ordering (Up to 32 Locations).
INFO:SoC:IRQ Handler (up to 32 Locations).
INFO:SoC:-------------------------------------------------------------------------------- INFO:SoCBusHandler:io0 Region added at Origin: 0x80000000, Size: 0x80000000, Mode: RW, Cached: False Linker: False.
INFO:SoC:CPU overriding sram mapping from 0x01000000 to 0x10000000.
INFO:SoCBusHandler:cpu_bus0 added as Bus Master.
INFO:SoCBusHandler:cpu_bus1 added as Bus Master.
INFO:SoCRegion:Region size rounded internally from 0x0000a000 to 0x00010000.
INFO:SoCBusHandler:rom Region added at Origin: 0x00000000, Size: 0x0000a000, Mode: R, Cached: True Linker: False.
INFO:SoCBusHandler:rom added as Bus Slave.
INFO:SoC:RAM rom added Origin: 0x00000000, Size: 0x0000a000, Mode: R, Cached: True Linker: False.
INFO:SoCBusHandler:sram Region added at Origin: 0x10000000, Size: 0x00002000, Mode: RW, Cached: True Linker: False.
INFO:SoCBusHandler:sram added as Bus Slave.
INFO:SoC:RAM sram added Origin: 0x10000000, Size: 0x00002000, Mode: RW, Cached: True Linker: False.
INFO:SoCBusHandler:main_ram Region added at Origin: 0x40000000, Size: 0x00004000, Mode: RW, Cached: True Linker: False.
INFO:SoCBusHandler:main_ram added as Bus Slave.
INFO:SoC:RAM main_ram added Origin: 0x40000000, Size: 0x00004000, Mode: RW, Cached: True Linker: False.
INFO:SoCIRQHandler:uart IRQ allocated at Location 0.
INFO:SoCIRQHandler:timer0 IRQ allocated at Location 1.
Traceback (most recent call last):
  File "C:/msys64/mingw64/lib/python3.9/runpy.py", line 197, in _run_module_as_main
    return _run_code(code, main_globals, None,
  File "C:/msys64/mingw64/lib/python3.9/runpy.py", line 87, in _run_code
    exec(code, run_globals)
  File "C:/msys64\home\William\Projects\FPGA\litex\SoCs\orangecrab-feather/orangecrab_feather/__main__.py", line 73, in <module>
    main()
  File "C:/msys64\home\William\Projects\FPGA\litex\SoCs\orangecrab-feather/orangecrab_feather/__main__.py", line 32, in main
    soc = FeatherSoC(
  File "C:/msys64\home\William\Projects\FPGA\litex\SoCs\orangecrab-feather/orangecrab_feather/feather_soc.py", line 167, in __init__
    self.uart.add_auto_tx_flush(sys_clk_freq=sys_clk_freq, timeout=1, interval=128)
  File "c:/msys64/home/william/projects/fpga/omigen/migen/migen/fhdl/module.py", line 136, in __getattr__
    raise AttributeError("'"+self.__class__.__name__+"' object has no attribute '"+name+"'")
AttributeError: 'CDCUsb' object has no attribute 'add_auto_tx_flush'