/* Generated by Yosys 0.35+39 (git sha1 031ad38b5, sccache x86_64-w64-mingw32-g++ 13.2.0 -Os) */

(* generator = "Amaranth" *)
module \top.leds (gpio__0__i, gpio__0__oe, gpio__0__o, gpio__1__i, gpio__1__oe, gpio__1__o, rst, clk, bus__addr, bus__r_data, bus__r_stb, bus__w_data, bus__w_stb, leds);
  wire _000_;
  wire _001_;
  wire _002_;
  wire _003_;
  wire _004_;
  wire _005_;
  wire _006_;
  wire _007_;
  wire _008_;
  wire _009_;
  wire _010_;
  wire _011_;
  wire _012_;
  wire _013_;
  wire _014_;
  wire _015_;
  wire _016_;
  wire _017_;
  wire _018_;
  wire _019_;
  wire _020_;
  wire _021_;
  wire _022_;
  wire _023_;
  wire _024_;
  wire _025_;
  wire _026_;
  wire _027_;
  wire _028_;
  wire _029_;
  wire _030_;
  wire _031_;
  wire _032_;
  wire _033_;
  wire _034_;
  wire _035_;
  wire _036_;
  wire _037_;
  wire _038_;
  wire _039_;
  wire _040_;
  wire _041_;
  wire _042_;
  wire _043_;
  wire _044_;
  wire _045_;
  wire _046_;
  wire _047_;
  wire _048_;
  wire _049_;
  wire _050_;
  wire _051_;
  wire _052_;
  wire _053_;
  wire _054_;
  wire _055_;
  wire _056_;
  wire _057_;
  wire _058_;
  wire _059_;
  wire [7:0] _060_;
  wire _061_;
  wire [7:0] _062_;
  wire _063_;
  wire _064_;
  wire _065_;
  wire _066_;
  wire _067_;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/.venv/lib/python3.11/site-packages/amaranth/lib/wiring.py:227" *)
  input [1:0] bus__addr;
  wire [1:0] bus__addr;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/.venv/lib/python3.11/site-packages/amaranth/lib/wiring.py:227" *)
  output [7:0] bus__r_data;
  wire [7:0] bus__r_data;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/.venv/lib/python3.11/site-packages/amaranth/lib/wiring.py:227" *)
  input bus__r_stb;
  wire bus__r_stb;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/.venv/lib/python3.11/site-packages/amaranth/lib/wiring.py:227" *)
  input [7:0] bus__w_data;
  wire [7:0] bus__w_data;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/.venv/lib/python3.11/site-packages/amaranth/lib/wiring.py:227" *)
  input bus__w_stb;
  wire bus__w_stb;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/.venv/lib/python3.11/site-packages/amaranth/vendor/_lattice_ice40.py:413" *)
  input clk;
  wire clk;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/.venv/lib/python3.11/site-packages/amaranth/lib/wiring.py:227" *)
  input gpio__0__i;
  wire gpio__0__i;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/.venv/lib/python3.11/site-packages/amaranth/lib/wiring.py:227" *)
  output gpio__0__o;
  reg gpio__0__o = 1'h0;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/.venv/lib/python3.11/site-packages/amaranth/lib/wiring.py:227" *)
  wire \gpio__0__o$next ;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/.venv/lib/python3.11/site-packages/amaranth/lib/wiring.py:227" *)
  output gpio__0__oe;
  reg gpio__0__oe = 1'h0;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/.venv/lib/python3.11/site-packages/amaranth/lib/wiring.py:227" *)
  wire \gpio__0__oe$next ;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/.venv/lib/python3.11/site-packages/amaranth/lib/wiring.py:227" *)
  input gpio__1__i;
  wire gpio__1__i;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/.venv/lib/python3.11/site-packages/amaranth/lib/wiring.py:227" *)
  output gpio__1__o;
  reg gpio__1__o = 1'h0;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/.venv/lib/python3.11/site-packages/amaranth/lib/wiring.py:227" *)
  wire \gpio__1__o$next ;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/.venv/lib/python3.11/site-packages/amaranth/lib/wiring.py:227" *)
  output gpio__1__oe;
  reg gpio__1__oe = 1'h0;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/.venv/lib/python3.11/site-packages/amaranth/lib/wiring.py:227" *)
  wire \gpio__1__oe$next ;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/.venv/lib/python3.11/site-packages/amaranth/lib/wiring.py:227" *)
  wire gpio__2__i;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/.venv/lib/python3.11/site-packages/amaranth/lib/wiring.py:227" *)
  reg gpio__2__o = 1'h0;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/.venv/lib/python3.11/site-packages/amaranth/lib/wiring.py:227" *)
  wire \gpio__2__o$next ;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/.venv/lib/python3.11/site-packages/amaranth/lib/wiring.py:227" *)
  reg gpio__2__oe = 1'h0;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/.venv/lib/python3.11/site-packages/amaranth/lib/wiring.py:227" *)
  wire \gpio__2__oe$next ;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/.venv/lib/python3.11/site-packages/amaranth/lib/wiring.py:227" *)
  wire gpio__3__i;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/.venv/lib/python3.11/site-packages/amaranth/lib/wiring.py:227" *)
  reg gpio__3__o = 1'h0;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/.venv/lib/python3.11/site-packages/amaranth/lib/wiring.py:227" *)
  wire \gpio__3__o$next ;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/.venv/lib/python3.11/site-packages/amaranth/lib/wiring.py:227" *)
  reg gpio__3__oe = 1'h0;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/.venv/lib/python3.11/site-packages/amaranth/lib/wiring.py:227" *)
  wire \gpio__3__oe$next ;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/.venv/lib/python3.11/site-packages/amaranth/lib/wiring.py:227" *)
  wire gpio__4__i;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/.venv/lib/python3.11/site-packages/amaranth/lib/wiring.py:227" *)
  reg gpio__4__o = 1'h0;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/.venv/lib/python3.11/site-packages/amaranth/lib/wiring.py:227" *)
  wire \gpio__4__o$next ;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/.venv/lib/python3.11/site-packages/amaranth/lib/wiring.py:227" *)
  reg gpio__4__oe = 1'h0;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/.venv/lib/python3.11/site-packages/amaranth/lib/wiring.py:227" *)
  wire \gpio__4__oe$next ;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/.venv/lib/python3.11/site-packages/amaranth/lib/wiring.py:227" *)
  wire gpio__5__i;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/.venv/lib/python3.11/site-packages/amaranth/lib/wiring.py:227" *)
  reg gpio__5__o = 1'h0;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/.venv/lib/python3.11/site-packages/amaranth/lib/wiring.py:227" *)
  wire \gpio__5__o$next ;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/.venv/lib/python3.11/site-packages/amaranth/lib/wiring.py:227" *)
  reg gpio__5__oe = 1'h0;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/.venv/lib/python3.11/site-packages/amaranth/lib/wiring.py:227" *)
  wire \gpio__5__oe$next ;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/.venv/lib/python3.11/site-packages/amaranth/lib/wiring.py:227" *)
  wire gpio__6__i;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/.venv/lib/python3.11/site-packages/amaranth/lib/wiring.py:227" *)
  reg gpio__6__o = 1'h0;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/.venv/lib/python3.11/site-packages/amaranth/lib/wiring.py:227" *)
  wire \gpio__6__o$next ;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/.venv/lib/python3.11/site-packages/amaranth/lib/wiring.py:227" *)
  reg gpio__6__oe = 1'h0;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/.venv/lib/python3.11/site-packages/amaranth/lib/wiring.py:227" *)
  wire \gpio__6__oe$next ;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/.venv/lib/python3.11/site-packages/amaranth/lib/wiring.py:227" *)
  wire gpio__7__i;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/.venv/lib/python3.11/site-packages/amaranth/lib/wiring.py:227" *)
  reg gpio__7__o = 1'h0;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/.venv/lib/python3.11/site-packages/amaranth/lib/wiring.py:227" *)
  wire \gpio__7__o$next ;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/.venv/lib/python3.11/site-packages/amaranth/lib/wiring.py:227" *)
  reg gpio__7__oe = 1'h0;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/.venv/lib/python3.11/site-packages/amaranth/lib/wiring.py:227" *)
  wire \gpio__7__oe$next ;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/.venv/lib/python3.11/site-packages/amaranth/lib/wiring.py:227" *)
  output [7:0] leds;
  reg [7:0] leds = 8'h00;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/.venv/lib/python3.11/site-packages/amaranth/lib/wiring.py:227" *)
  wire [7:0] \leds$next ;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/.venv/lib/python3.11/site-packages/amaranth/lib/wiring.py:227" *)
  wire [1:0] mux_bus__addr;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/.venv/lib/python3.11/site-packages/amaranth/lib/wiring.py:227" *)
  wire [7:0] mux_bus__r_data;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/.venv/lib/python3.11/site-packages/amaranth/lib/wiring.py:227" *)
  wire mux_bus__r_stb;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/.venv/lib/python3.11/site-packages/amaranth/lib/wiring.py:227" *)
  wire [7:0] mux_bus__w_data;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/.venv/lib/python3.11/site-packages/amaranth/lib/wiring.py:227" *)
  wire mux_bus__w_stb;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/.venv/lib/python3.11/site-packages/amaranth/lib/wiring.py:227" *)
  wire [7:0] mux_inout__r_data;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/.venv/lib/python3.11/site-packages/amaranth/lib/wiring.py:227" *)
  wire mux_inout__w_stb;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/.venv/lib/python3.11/site-packages/amaranth/lib/wiring.py:227" *)
  wire [7:0] mux_leds__w_data;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/.venv/lib/python3.11/site-packages/amaranth/lib/wiring.py:227" *)
  wire mux_leds__w_stb;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/.venv/lib/python3.11/site-packages/amaranth/lib/wiring.py:227" *)
  wire [7:0] mux_oe__w_data;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/.venv/lib/python3.11/site-packages/amaranth/lib/wiring.py:227" *)
  wire mux_oe__w_stb;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/.venv/lib/python3.11/site-packages/amaranth/vendor/_lattice_ice40.py:413" *)
  input rst;
  wire rst;
  always @(posedge clk)
    leds <= \leds$next ;
  always @(posedge clk)
    gpio__0__oe <= \gpio__0__oe$next ;
  always @(posedge clk)
    gpio__1__oe <= \gpio__1__oe$next ;
  always @(posedge clk)
    gpio__2__oe <= \gpio__2__oe$next ;
  always @(posedge clk)
    gpio__3__oe <= \gpio__3__oe$next ;
  always @(posedge clk)
    gpio__4__oe <= \gpio__4__oe$next ;
  always @(posedge clk)
    gpio__5__oe <= \gpio__5__oe$next ;
  always @(posedge clk)
    gpio__6__oe <= \gpio__6__oe$next ;
  always @(posedge clk)
    gpio__7__oe <= \gpio__7__oe$next ;
  always @(posedge clk)
    gpio__0__o <= \gpio__0__o$next ;
  always @(posedge clk)
    gpio__1__o <= \gpio__1__o$next ;
  always @(posedge clk)
    gpio__2__o <= \gpio__2__o$next ;
  always @(posedge clk)
    gpio__3__o <= \gpio__3__o$next ;
  always @(posedge clk)
    gpio__4__o <= \gpio__4__o$next ;
  always @(posedge clk)
    gpio__5__o <= \gpio__5__o$next ;
  always @(posedge clk)
    gpio__6__o <= \gpio__6__o$next ;
  always @(posedge clk)
    gpio__7__o <= \gpio__7__o$next ;
  assign _010_ = _021_ ? (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/examples/attosoc.py:135" *) mux_oe__w_data[7] : gpio__7__oe;
  assign _001_ = _002_ ? (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/.venv/lib/python3.11/site-packages/amaranth/hdl/xfrm.py:503" *) 1'h0 : _067_;
  assign _003_ = _004_ ? (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/examples/attosoc.py:135" *) mux_oe__w_data[4] : gpio__4__oe;
  assign _005_ = _006_ ? (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/.venv/lib/python3.11/site-packages/amaranth/hdl/xfrm.py:503" *) 1'h0 : _003_;
  assign _007_ = _008_ ? (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/examples/attosoc.py:135" *) mux_oe__w_data[3] : gpio__3__oe;
  assign _009_ = _011_ ? (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/.venv/lib/python3.11/site-packages/amaranth/hdl/xfrm.py:503" *) 1'h0 : _007_;
  assign _012_ = _013_ ? (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/examples/attosoc.py:135" *) mux_oe__w_data[2] : gpio__2__oe;
  assign _014_ = _015_ ? (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/.venv/lib/python3.11/site-packages/amaranth/hdl/xfrm.py:503" *) 1'h0 : _012_;
  assign _016_ = _017_ ? (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/examples/attosoc.py:135" *) mux_oe__w_data[1] : gpio__1__oe;
  assign _018_ = _019_ ? (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/.venv/lib/python3.11/site-packages/amaranth/hdl/xfrm.py:503" *) 1'h0 : _016_;
  assign _020_ = _022_ ? (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/examples/attosoc.py:135" *) mux_oe__w_data[0] : gpio__0__oe;
  assign _032_ = _043_ ? (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/.venv/lib/python3.11/site-packages/amaranth/hdl/xfrm.py:503" *) 1'h0 : _010_;
  assign _023_ = _024_ ? (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/.venv/lib/python3.11/site-packages/amaranth/hdl/xfrm.py:503" *) 1'h0 : _020_;
  assign _025_ = _026_ ? (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/examples/attosoc.py:128" *) mux_leds__w_data[7] : gpio__7__o;
  assign _027_ = _028_ ? (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/.venv/lib/python3.11/site-packages/amaranth/hdl/xfrm.py:503" *) 1'h0 : _025_;
  assign _029_ = _030_ ? (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/examples/attosoc.py:128" *) mux_leds__w_data[6] : gpio__6__o;
  assign _031_ = _033_ ? (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/.venv/lib/python3.11/site-packages/amaranth/hdl/xfrm.py:503" *) 1'h0 : _029_;
  assign _034_ = _035_ ? (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/examples/attosoc.py:128" *) mux_leds__w_data[5] : gpio__5__o;
  assign _036_ = _037_ ? (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/.venv/lib/python3.11/site-packages/amaranth/hdl/xfrm.py:503" *) 1'h0 : _034_;
  assign _038_ = _039_ ? (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/examples/attosoc.py:128" *) mux_leds__w_data[4] : gpio__4__o;
  assign _040_ = _041_ ? (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/.venv/lib/python3.11/site-packages/amaranth/hdl/xfrm.py:503" *) 1'h0 : _038_;
  assign _042_ = _044_ ? (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/examples/attosoc.py:128" *) mux_leds__w_data[3] : gpio__3__o;
  assign _054_ = _064_ ? (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/examples/attosoc.py:135" *) mux_oe__w_data[6] : gpio__6__oe;
  assign _045_ = _046_ ? (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/.venv/lib/python3.11/site-packages/amaranth/hdl/xfrm.py:503" *) 1'h0 : _042_;
  assign _047_ = _048_ ? (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/examples/attosoc.py:128" *) mux_leds__w_data[2] : gpio__2__o;
  assign _049_ = _050_ ? (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/.venv/lib/python3.11/site-packages/amaranth/hdl/xfrm.py:503" *) 1'h0 : _047_;
  assign _051_ = _052_ ? (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/examples/attosoc.py:128" *) mux_leds__w_data[1] : gpio__1__o;
  assign _053_ = _055_ ? (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/.venv/lib/python3.11/site-packages/amaranth/hdl/xfrm.py:503" *) 1'h0 : _051_;
  assign _056_ = _057_ ? (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/examples/attosoc.py:128" *) mux_leds__w_data[0] : gpio__0__o;
  assign _058_ = _059_ ? (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/.venv/lib/python3.11/site-packages/amaranth/hdl/xfrm.py:503" *) 1'h0 : _056_;
  assign _060_ = _061_ ? (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/examples/attosoc.py:125" *) mux_leds__w_data : leds;
  assign _062_ = _063_ ? (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/.venv/lib/python3.11/site-packages/amaranth/hdl/xfrm.py:503" *) 8'h00 : _060_;
  assign _065_ = _066_ ? (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/.venv/lib/python3.11/site-packages/amaranth/hdl/xfrm.py:503" *) 1'h0 : _054_;
  assign _067_ = _000_ ? (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/examples/attosoc.py:135" *) mux_oe__w_data[5] : gpio__5__oe;
  \top.leds.mux  mux (
    .bus__addr(mux_bus__addr),
    .bus__r_data(mux_bus__r_data),
    .bus__r_stb(mux_bus__r_stb),
    .bus__w_data(mux_bus__w_data),
    .bus__w_stb(mux_bus__w_stb),
    .clk(clk),
    .inout__r_data(mux_inout__r_data),
    .inout__w_stb(mux_inout__w_stb),
    .leds__w_data(mux_leds__w_data),
    .leds__w_stb(mux_leds__w_stb),
    .oe__w_data(mux_oe__w_data),
    .oe__w_stb(mux_oe__w_stb),
    .rst(rst)
  );
  assign gpio__2__i = 1'h0;
  assign gpio__3__i = 1'h0;
  assign gpio__4__i = 1'h0;
  assign gpio__5__i = 1'h0;
  assign gpio__6__i = 1'h0;
  assign gpio__7__i = 1'h0;
  assign mux_inout__r_data[7] = 1'h0;
  assign mux_inout__r_data[6] = 1'h0;
  assign mux_inout__r_data[5] = 1'h0;
  assign mux_inout__r_data[4] = 1'h0;
  assign mux_inout__r_data[3] = 1'h0;
  assign mux_inout__r_data[2] = 1'h0;
  assign mux_inout__r_data[1] = gpio__1__i;
  assign mux_inout__r_data[0] = gpio__0__i;
  assign mux_bus__w_stb = bus__w_stb;
  assign mux_bus__w_data = bus__w_data;
  assign mux_bus__r_stb = bus__r_stb;
  assign bus__r_data = mux_bus__r_data;
  assign mux_bus__addr = bus__addr;
  assign _021_ = mux_oe__w_stb;
  assign _043_ = rst;
  assign \gpio__7__oe$next  = _032_;
  assign _064_ = mux_oe__w_stb;
  assign _066_ = rst;
  assign \gpio__6__oe$next  = _065_;
  assign _000_ = mux_oe__w_stb;
  assign _002_ = rst;
  assign \gpio__5__oe$next  = _001_;
  assign _004_ = mux_oe__w_stb;
  assign _006_ = rst;
  assign \gpio__4__oe$next  = _005_;
  assign _008_ = mux_oe__w_stb;
  assign _011_ = rst;
  assign \gpio__3__oe$next  = _009_;
  assign _013_ = mux_oe__w_stb;
  assign _015_ = rst;
  assign \gpio__2__oe$next  = _014_;
  assign _017_ = mux_oe__w_stb;
  assign _019_ = rst;
  assign \gpio__1__oe$next  = _018_;
  assign _022_ = mux_oe__w_stb;
  assign _024_ = rst;
  assign \gpio__0__oe$next  = _023_;
  assign _026_ = mux_inout__w_stb;
  assign _028_ = rst;
  assign \gpio__7__o$next  = _027_;
  assign _030_ = mux_inout__w_stb;
  assign _033_ = rst;
  assign \gpio__6__o$next  = _031_;
  assign _035_ = mux_inout__w_stb;
  assign _037_ = rst;
  assign \gpio__5__o$next  = _036_;
  assign _039_ = mux_inout__w_stb;
  assign _041_ = rst;
  assign \gpio__4__o$next  = _040_;
  assign _044_ = mux_inout__w_stb;
  assign _046_ = rst;
  assign \gpio__3__o$next  = _045_;
  assign _048_ = mux_inout__w_stb;
  assign _050_ = rst;
  assign \gpio__2__o$next  = _049_;
  assign _052_ = mux_inout__w_stb;
  assign _055_ = rst;
  assign \gpio__1__o$next  = _053_;
  assign _057_ = mux_inout__w_stb;
  assign _059_ = rst;
  assign \gpio__0__o$next  = _058_;
  assign _061_ = mux_leds__w_stb;
  assign _063_ = rst;
  assign \leds$next  = _062_;
endmodule

(* generator = "Amaranth" *)
module \top.leds.mux (clk, bus__addr, bus__r_data, bus__r_stb, bus__w_data, bus__w_stb, leds__w_stb, leds__w_data, inout__w_stb, inout__r_data, oe__w_stb, oe__w_data, rst);
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/.venv/lib/python3.11/site-packages/amaranth_soc/csr/bus.py:636" *)
  wire _00_;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/.venv/lib/python3.11/site-packages/amaranth_soc/csr/bus.py:637" *)
  wire [7:0] _01_;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/.venv/lib/python3.11/site-packages/amaranth_soc/csr/bus.py:643" *)
  wire [7:0] _02_;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/.venv/lib/python3.11/site-packages/amaranth_soc/csr/bus.py:643" *)
  wire [7:0] _03_;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/.venv/lib/python3.11/site-packages/amaranth_soc/csr/bus.py:636" *)
  wire _04_;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/.venv/lib/python3.11/site-packages/amaranth_soc/csr/bus.py:637" *)
  wire [7:0] _05_;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/.venv/lib/python3.11/site-packages/amaranth_soc/csr/bus.py:637" *)
  wire [7:0] _06_;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/.venv/lib/python3.11/site-packages/amaranth_soc/csr/bus.py:637" *)
  wire [7:0] _07_;
  wire _08_;
  wire _09_;
  wire [7:0] _10_;
  wire _11_;
  wire [7:0] _12_;
  wire _13_;
  wire _14_;
  wire _15_;
  wire _16_;
  wire _17_;
  wire _18_;
  wire _19_;
  wire _20_;
  wire _21_;
  wire _22_;
  wire _23_;
  wire _24_;
  wire _25_;
  wire _26_;
  wire _27_;
  wire _28_;
  wire _29_;
  wire [7:0] _30_;
  wire _31_;
  wire [7:0] _32_;
  wire _33_;
  wire _34_;
  wire _35_;
  wire _36_;
  wire _37_;
  wire _38_;
  wire _39_;
  wire _40_;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/.venv/lib/python3.11/site-packages/amaranth/lib/wiring.py:227" *)
  input [1:0] bus__addr;
  wire [1:0] bus__addr;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/.venv/lib/python3.11/site-packages/amaranth/lib/wiring.py:227" *)
  output [7:0] bus__r_data;
  wire [7:0] bus__r_data;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/.venv/lib/python3.11/site-packages/amaranth/lib/wiring.py:227" *)
  input bus__r_stb;
  wire bus__r_stb;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/.venv/lib/python3.11/site-packages/amaranth/lib/wiring.py:227" *)
  input [7:0] bus__w_data;
  wire [7:0] bus__w_data;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/.venv/lib/python3.11/site-packages/amaranth/lib/wiring.py:227" *)
  input bus__w_stb;
  wire bus__w_stb;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/.venv/lib/python3.11/site-packages/amaranth/vendor/_lattice_ice40.py:413" *)
  input clk;
  wire clk;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/.venv/lib/python3.11/site-packages/amaranth/lib/wiring.py:227" *)
  input [7:0] inout__r_data;
  wire [7:0] inout__r_data;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/.venv/lib/python3.11/site-packages/amaranth/lib/wiring.py:227" *)
  wire inout__r_stb;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/.venv/lib/python3.11/site-packages/amaranth/lib/wiring.py:227" *)
  wire [7:0] inout__w_data;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/.venv/lib/python3.11/site-packages/amaranth/lib/wiring.py:227" *)
  output inout__w_stb;
  reg inout__w_stb = 1'h0;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/.venv/lib/python3.11/site-packages/amaranth/lib/wiring.py:227" *)
  wire \inout__w_stb$next ;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/.venv/lib/python3.11/site-packages/amaranth/lib/wiring.py:227" *)
  output [7:0] leds__w_data;
  wire [7:0] leds__w_data;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/.venv/lib/python3.11/site-packages/amaranth/lib/wiring.py:227" *)
  output leds__w_stb;
  reg leds__w_stb = 1'h0;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/.venv/lib/python3.11/site-packages/amaranth/lib/wiring.py:227" *)
  wire \leds__w_stb$next ;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/.venv/lib/python3.11/site-packages/amaranth/lib/wiring.py:227" *)
  wire [7:0] oe__r_data;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/.venv/lib/python3.11/site-packages/amaranth/lib/wiring.py:227" *)
  wire oe__r_stb;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/.venv/lib/python3.11/site-packages/amaranth/lib/wiring.py:227" *)
  output [7:0] oe__w_data;
  wire [7:0] oe__w_data;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/.venv/lib/python3.11/site-packages/amaranth/lib/wiring.py:227" *)
  output oe__w_stb;
  reg oe__w_stb = 1'h0;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/.venv/lib/python3.11/site-packages/amaranth/lib/wiring.py:227" *)
  wire \oe__w_stb$next ;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/.venv/lib/python3.11/site-packages/amaranth_soc/csr/bus.py:343" *)
  reg [7:0] r_shadow__0__data = 8'h00;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/.venv/lib/python3.11/site-packages/amaranth_soc/csr/bus.py:343" *)
  wire [7:0] \r_shadow__0__data$next ;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/.venv/lib/python3.11/site-packages/amaranth_soc/csr/bus.py:344" *)
  reg r_shadow__0__r_en = 1'h0;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/.venv/lib/python3.11/site-packages/amaranth_soc/csr/bus.py:344" *)
  wire \r_shadow__0__r_en$next ;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/.venv/lib/python3.11/site-packages/amaranth_soc/csr/bus.py:345" *)
  wire r_shadow__0__w_en;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/.venv/lib/python3.11/site-packages/amaranth/vendor/_lattice_ice40.py:413" *)
  input rst;
  wire rst;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/.venv/lib/python3.11/site-packages/amaranth_soc/csr/bus.py:343" *)
  reg [7:0] w_shadow__0__data = 8'h00;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/.venv/lib/python3.11/site-packages/amaranth_soc/csr/bus.py:343" *)
  wire [7:0] \w_shadow__0__data$next ;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/.venv/lib/python3.11/site-packages/amaranth_soc/csr/bus.py:345" *)
  wire w_shadow__0__w_en;
  assign _02_ = r_shadow__0__r_en ? (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/.venv/lib/python3.11/site-packages/amaranth_soc/csr/bus.py:643" *) r_shadow__0__data : 8'h00;
  always @(posedge clk)
    r_shadow__0__r_en <= \r_shadow__0__r_en$next ;
  always @(posedge clk)
    r_shadow__0__data <= \r_shadow__0__data$next ;
  always @(posedge clk)
    inout__w_stb <= \inout__w_stb$next ;
  always @(posedge clk)
    oe__w_stb <= \oe__w_stb$next ;
  always @(posedge clk)
    leds__w_stb <= \leds__w_stb$next ;
  always @(posedge clk)
    w_shadow__0__data <= \w_shadow__0__data$next ;
  assign _04_ = _00_ | (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/.venv/lib/python3.11/site-packages/amaranth_soc/csr/bus.py:636" *) oe__r_stb;
  assign _05_ = inout__r_stb ? (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/.venv/lib/python3.11/site-packages/amaranth_soc/csr/bus.py:637" *) inout__r_data : 8'h00;
  assign _08_ = _09_ ? (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/.venv/lib/python3.11/site-packages/amaranth/hdl/xfrm.py:503" *) 1'h0 : _38_;
  assign _10_ = _11_ ? (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/.venv/lib/python3.11/site-packages/amaranth_soc/csr/bus.py:667" *) bus__w_data : w_shadow__0__data;
  assign _12_ = _13_ ? (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/.venv/lib/python3.11/site-packages/amaranth/hdl/xfrm.py:503" *) 8'h00 : _10_;
  function [0:0] _53_;
    input [0:0] a;
    input [2:0] b;
    input [2:0] s;
    (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/.venv/lib/python3.11/site-packages/amaranth_soc/csr/bus.py:648" *)
    (* parallel_case *)
    casez (s)
      3'b??1:
        _53_ = b[0:0];
      3'b?1?:
        _53_ = b[1:1];
      3'b1??:
        _53_ = b[2:2];
      default:
        _53_ = a;
    endcase
  endfunction
  assign _14_ = _53_(1'h0, { bus__w_stb, bus__w_stb, bus__w_stb }, { _17_, _16_, _15_ });
  assign _15_ = ! (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/.venv/lib/python3.11/site-packages/amaranth_soc/csr/bus.py:648" *) bus__addr;
  assign _16_ = bus__addr == (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/.venv/lib/python3.11/site-packages/amaranth_soc/csr/bus.py:648" *) 2'h2;
  assign _17_ = bus__addr == (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/.venv/lib/python3.11/site-packages/amaranth_soc/csr/bus.py:648" *) 2'h1;
  assign _18_ = _19_ ? (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/.venv/lib/python3.11/site-packages/amaranth_soc/csr/bus.py:648" *) bus__w_stb : 1'h0;
  assign _19_ = ! (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/.venv/lib/python3.11/site-packages/amaranth_soc/csr/bus.py:648" *) bus__addr;
  assign _20_ = _21_ ? (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/.venv/lib/python3.11/site-packages/amaranth/hdl/xfrm.py:503" *) 1'h0 : _18_;
  assign _22_ = _23_ ? (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/.venv/lib/python3.11/site-packages/amaranth_soc/csr/bus.py:648" *) bus__w_stb : 1'h0;
  assign _23_ = bus__addr == (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/.venv/lib/python3.11/site-packages/amaranth_soc/csr/bus.py:648" *) 2'h2;
  assign _24_ = _25_ ? (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/.venv/lib/python3.11/site-packages/amaranth/hdl/xfrm.py:503" *) 1'h0 : _22_;
  assign _26_ = _27_ ? (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/.venv/lib/python3.11/site-packages/amaranth_soc/csr/bus.py:648" *) bus__w_stb : 1'h0;
  assign _27_ = bus__addr == (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/.venv/lib/python3.11/site-packages/amaranth_soc/csr/bus.py:648" *) 2'h1;
  assign _28_ = _29_ ? (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/.venv/lib/python3.11/site-packages/amaranth/hdl/xfrm.py:503" *) 1'h0 : _26_;
  assign _30_ = _31_ ? (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/.venv/lib/python3.11/site-packages/amaranth_soc/csr/bus.py:640" *) _01_ : r_shadow__0__data;
  assign _32_ = _33_ ? (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/.venv/lib/python3.11/site-packages/amaranth/hdl/xfrm.py:503" *) 8'h00 : _30_;
  assign _34_ = _35_ ? (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/.venv/lib/python3.11/site-packages/amaranth_soc/csr/bus.py:623" *) bus__r_stb : 1'h0;
  assign _35_ = bus__addr == (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/.venv/lib/python3.11/site-packages/amaranth_soc/csr/bus.py:623" *) 2'h2;
  assign _36_ = _37_ ? (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/.venv/lib/python3.11/site-packages/amaranth_soc/csr/bus.py:623" *) bus__r_stb : 1'h0;
  assign _37_ = bus__addr == (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/.venv/lib/python3.11/site-packages/amaranth_soc/csr/bus.py:623" *) 2'h1;
  function [0:0] _72_;
    input [0:0] a;
    input [1:0] b;
    input [1:0] s;
    (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/.venv/lib/python3.11/site-packages/amaranth_soc/csr/bus.py:623" *)
    (* parallel_case *)
    casez (s)
      2'b?1:
        _72_ = b[0:0];
      2'b1?:
        _72_ = b[1:1];
      default:
        _72_ = a;
    endcase
  endfunction
  assign _38_ = _72_(1'h0, { bus__r_stb, bus__r_stb }, { _40_, _39_ });
  assign _39_ = bus__addr == (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/.venv/lib/python3.11/site-packages/amaranth_soc/csr/bus.py:623" *) 2'h2;
  assign _40_ = bus__addr == (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/.venv/lib/python3.11/site-packages/amaranth_soc/csr/bus.py:623" *) 2'h1;
  assign oe__r_data = 8'h00;
  assign leds__w_data = w_shadow__0__data;
  assign oe__w_data = w_shadow__0__data;
  assign inout__w_data = w_shadow__0__data;
  assign bus__r_data = _03_;
  assign r_shadow__0__w_en = _04_;
  assign _11_ = w_shadow__0__w_en;
  assign _13_ = rst;
  assign \w_shadow__0__data$next  = _12_;
  assign w_shadow__0__w_en = _14_;
  assign _21_ = rst;
  assign \leds__w_stb$next  = _20_;
  assign _25_ = rst;
  assign \oe__w_stb$next  = _24_;
  assign _29_ = rst;
  assign \inout__w_stb$next  = _28_;
  assign _31_ = r_shadow__0__w_en;
  assign _33_ = rst;
  assign \r_shadow__0__data$next  = _32_;
  assign oe__r_stb = _34_;
  assign inout__r_stb = _36_;
  assign _09_ = rst;
  assign \r_shadow__0__r_en$next  = _08_;
  assign _00_ = _36_;
  assign _06_ = _05_;
  assign _07_ = 8'h00;
  assign _01_ = _05_;
  assign _03_ = _02_;
endmodule