from migen import *

from litex.gen.fhdl import verilog
from litex.soc.cores.uart import UART, UARTPHY, UARTPads

# uart_pads = UARTPads()
# uart_phy = UARTPHY(uart_pads, clk_freq=96000, baudrate=9600)
# uart = UART(uart_phy)
uart = UART()

full_uart = Module()
# full_uart.submodules += [uart_phy, uart]
full_uart.submodules += uart
full_uart.clock_domains += ClockDomain("sys")

with open("uart.v", "w") as fp:
    fp.write(str(verilog.convert(full_uart,
                                 ios={# uart_pads.tx,
                                      # uart_pads.rx,
                                      uart.source.valid,
                                      uart.source.ready,
                                      uart.source.first,
                                      uart.source.last,
                                      uart.source.data,
                                      uart.sink.valid,
                                      uart.sink.ready,
                                      uart.sink.first,
                                      uart.sink.last,
                                      uart.sink.data,
                                      })))