def find_module_create_verilog(module, width, register=True):
    mod_name, cls_name = module.split(":")
    cls = getattr(importlib.import_module(mod_name), cls_name)  # noqa: E501

    p = inspect.signature(cls.__init__).parameters
    kwargs = dict()
    if "width" in p:
        kwargs["width"] = width

    m = cls(**kwargs)
    if not isinstance(m, Elaboratable):
        raise ValueError(f"{cls} does not look like an Elaboratable")

    if register:
        w = Module()
        wrapper = PureInterface(m.signature)
        w.d.sync += connect(w, wrapper, flipped(m))
        v = convert(w)
    else:
        v = convert(m)

    return { "verilog": v }