/* Generated by Yosys 0.32+63 (git sha1 de54cf1a0, sccache x86_64-w64-mingw32-g++ 13.2.0 -Os) */

(* \amaranth.hierarchy  = "sequencer.U$$0" *)
(* generator = "Amaranth" *)
module \U$$0 (ctl__rd__data, ctl__rd__stb, efb__ack, efb__adr, efb__cyc, efb__dat_r, efb__dat_w, efb__stb, efb__we, ctl__req, ctl__cmd, ctl__done, ctl__op_len, ctl__data_len, ctl__xfer_is_wr, rst, clk, ctl__wr__data);
  reg \$auto$verilog_backend.cc:2184:dump_module$1  = 0;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:194" *)
  wire \$1 ;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:219" *)
  wire \$11 ;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:114" *)
  wire [6:0] \$13 ;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:251" *)
  wire [6:0] \$15 ;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:251" *)
  wire \$17 ;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:113" *)
  wire [2:0] \$19 ;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:212" *)
  wire [2:0] \$21 ;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:212" *)
  wire \$23 ;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:213" *)
  wire [2:0] \$25 ;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:213" *)
  wire [2:0] \$26 ;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:114" *)
  wire [6:0] \$28 ;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:196" *)
  wire \$3 ;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:246" *)
  wire [6:0] \$30 ;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:246" *)
  wire \$32 ;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:247" *)
  wire [6:0] \$34 ;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:247" *)
  wire [6:0] \$35 ;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:113" *)
  wire [2:0] \$5 ;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:217" *)
  wire [2:0] \$7 ;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:217" *)
  wire \$9 ;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/amaranth/build/__editable__.amaranth-0.4.dev183+gfc85feb-py3-none-any/amaranth/hdl/ir.py:532" *)
  input clk;
  wire clk;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/amaranth/build/__editable__.amaranth-0.4.dev183+gfc85feb-py3-none-any/amaranth/lib/wiring.py:227" *)
  input [31:0] ctl__cmd;
  wire [31:0] ctl__cmd;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/amaranth/build/__editable__.amaranth-0.4.dev183+gfc85feb-py3-none-any/amaranth/lib/wiring.py:227" *)
  input [5:0] ctl__data_len;
  wire [5:0] ctl__data_len;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/amaranth/build/__editable__.amaranth-0.4.dev183+gfc85feb-py3-none-any/amaranth/lib/wiring.py:227" *)
  output ctl__done;
  reg ctl__done;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/amaranth/build/__editable__.amaranth-0.4.dev183+gfc85feb-py3-none-any/amaranth/lib/wiring.py:227" *)
  input [1:0] ctl__op_len;
  wire [1:0] ctl__op_len;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/amaranth/build/__editable__.amaranth-0.4.dev183+gfc85feb-py3-none-any/amaranth/lib/wiring.py:227" *)
  output [7:0] ctl__rd__data;
  reg [7:0] ctl__rd__data = 8'h00;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/amaranth/build/__editable__.amaranth-0.4.dev183+gfc85feb-py3-none-any/amaranth/lib/wiring.py:227" *)
  reg [7:0] \ctl__rd__data$next ;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/amaranth/build/__editable__.amaranth-0.4.dev183+gfc85feb-py3-none-any/amaranth/lib/wiring.py:227" *)
  output ctl__rd__stb;
  reg ctl__rd__stb;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/amaranth/build/__editable__.amaranth-0.4.dev183+gfc85feb-py3-none-any/amaranth/lib/wiring.py:227" *)
  input ctl__req;
  wire ctl__req;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/amaranth/build/__editable__.amaranth-0.4.dev183+gfc85feb-py3-none-any/amaranth/lib/wiring.py:227" *)
  input [31:0] ctl__wr__data;
  wire [31:0] ctl__wr__data;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/amaranth/build/__editable__.amaranth-0.4.dev183+gfc85feb-py3-none-any/amaranth/lib/wiring.py:227" *)
  input ctl__xfer_is_wr;
  wire ctl__xfer_is_wr;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:114" *)
  reg [5:0] curr_data = 6'h00;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:114" *)
  reg [5:0] \curr_data$next ;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:113" *)
  reg [1:0] curr_op = 2'h0;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:113" *)
  reg [1:0] \curr_op$next ;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/amaranth/build/__editable__.amaranth-0.4.dev183+gfc85feb-py3-none-any/amaranth/lib/wiring.py:227" *)
  input efb__ack;
  wire efb__ack;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/amaranth/build/__editable__.amaranth-0.4.dev183+gfc85feb-py3-none-any/amaranth/lib/wiring.py:227" *)
  output [7:0] efb__adr;
  reg [7:0] efb__adr;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/amaranth/build/__editable__.amaranth-0.4.dev183+gfc85feb-py3-none-any/amaranth/lib/wiring.py:227" *)
  output efb__cyc;
  reg efb__cyc;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/amaranth/build/__editable__.amaranth-0.4.dev183+gfc85feb-py3-none-any/amaranth/lib/wiring.py:227" *)
  input [7:0] efb__dat_r;
  wire [7:0] efb__dat_r;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/amaranth/build/__editable__.amaranth-0.4.dev183+gfc85feb-py3-none-any/amaranth/lib/wiring.py:227" *)
  output [7:0] efb__dat_w;
  reg [7:0] efb__dat_w;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/amaranth/build/__editable__.amaranth-0.4.dev183+gfc85feb-py3-none-any/amaranth/lib/wiring.py:227" *)
  output efb__stb;
  reg efb__stb;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/amaranth/build/__editable__.amaranth-0.4.dev183+gfc85feb-py3-none-any/amaranth/lib/wiring.py:227" *)
  output efb__we;
  reg efb__we;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:161" *)
  reg [3:0] fsm_state = 4'h0;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:161" *)
  reg [3:0] \fsm_state$next ;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/amaranth/build/__editable__.amaranth-0.4.dev183+gfc85feb-py3-none-any/amaranth/hdl/ir.py:532" *)
  input rst;
  wire rst;
  assign \$9  = $signed(\$5 ) < (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:217" *) $signed(\$7 );
  assign \$11  = ctl__data_len > (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:219" *) 1'h0;
  assign \$13  = + (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:114" *) curr_data;
  assign \$15  = ctl__data_len - (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:251" *) 1'h1;
  assign \$17  = $signed(\$13 ) < (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:251" *) $signed(\$15 );
  assign \$1  = ctl__op_len > (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:194" *) 1'h0;
  assign \$19  = + (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:113" *) curr_op;
  assign \$21  = ctl__op_len - (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:212" *) 1'h1;
  assign \$23  = $signed(\$19 ) < (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:212" *) $signed(\$21 );
  assign \$26  = curr_op + (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:213" *) 1'h1;
  assign \$28  = + (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:114" *) curr_data;
  assign \$30  = ctl__data_len - (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:246" *) 1'h1;
  assign \$32  = $signed(\$28 ) < (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:246" *) $signed(\$30 );
  assign \$35  = curr_data + (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:247" *) 1'h1;
  always @(posedge clk)
    fsm_state <= \fsm_state$next ;
  always @(posedge clk)
    curr_op <= \curr_op$next ;
  always @(posedge clk)
    ctl__rd__data <= \ctl__rd__data$next ;
  assign \$3  = ctl__data_len > (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:196" *) 1'h0;
  always @(posedge clk)
    curr_data <= \curr_data$next ;
  assign \$5  = + (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:113" *) curr_op;
  assign \$7  = ctl__op_len - (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:217" *) 1'h1;
  always @* begin
    if (\$auto$verilog_backend.cc:2184:dump_module$1 ) begin end
    \fsm_state$next  = fsm_state;
    (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:161" *)
    casez (fsm_state)
      /* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:162" */
      /* \amaranth.decoding  = "IDLE/0" */
      4'h0:
          (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:117" *)
          casez (ctl__req)
            /* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:117" */
            1'h1:
                \fsm_state$next  = 4'h1;
          endcase
      /* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:165" */
      /* \amaranth.decoding  = "WB_ENABLE_1/1" */
      4'h1:
          (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:117" *)
          casez (efb__ack)
            /* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:117" */
            1'h1:
                \fsm_state$next  = 4'h2;
          endcase
      /* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:174" */
      /* \amaranth.decoding  = "WB_ENABLE_2/2" */
      4'h2:
          \fsm_state$next  = 4'h3;
      /* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:179" */
      /* \amaranth.decoding  = "WB_CMD_1/3" */
      4'h3:
          (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:117" *)
          casez (efb__ack)
            /* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:117" */
            1'h1:
                \fsm_state$next  = 4'h4;
          endcase
      /* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:188" */
      /* \amaranth.decoding  = "WB_CMD_2/4" */
      4'h4:
          (* full_case = 32'd1 *)
          (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:194" *)
          casez ({ \$3 , \$1  })
            /* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:194" */
            2'b?1:
                \fsm_state$next  = 4'h5;
            /* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:196" */
            2'b1?:
                \fsm_state$next  = 4'h6;
            /* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:198" */
            default:
                \fsm_state$next  = 4'h7;
          endcase
      /* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:201" */
      /* \amaranth.decoding  = "WB_OPERAND_1/5" */
      4'h5:
          (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:117" *)
          casez (efb__ack)
            /* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:117" */
            1'h1:
                \fsm_state$next  = 4'h8;
          endcase
      /* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:208" */
      /* \amaranth.decoding  = "WB_OPERAND_2/8" */
      4'h8:
          (* full_case = 32'd1 *)
          (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:217" *)
          casez ({ \$11 , \$9  })
            /* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:217" */
            2'b?1:
                \fsm_state$next  = 4'h5;
            /* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:219" */
            2'b1?:
                \fsm_state$next  = 4'h6;
            /* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:221" */
            default:
                \fsm_state$next  = 4'h7;
          endcase
      /* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:224" */
      /* \amaranth.decoding  = "WB_DATA_1/6" */
      4'h6:
          (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:117" *)
          casez (efb__ack)
            /* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:117" */
            1'h1:
                \fsm_state$next  = 4'h9;
          endcase
      /* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:238" */
      /* \amaranth.decoding  = "WB_DATA_2/9" */
      4'h9:
          (* full_case = 32'd1 *)
          (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:251" *)
          casez (\$17 )
            /* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:251" */
            1'h1:
                \fsm_state$next  = 4'h6;
            /* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:253" */
            default:
                \fsm_state$next  = 4'h7;
          endcase
      /* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:256" */
      /* \amaranth.decoding  = "WB_DISABLE_1/7" */
      4'h7:
          (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:117" *)
          casez (efb__ack)
            /* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:117" */
            1'h1:
                \fsm_state$next  = 4'ha;
          endcase
      /* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:262" */
      /* \amaranth.decoding  = "WB_DISABLE_2/10" */
      4'ha:
        begin
          \fsm_state$next  = 4'h0;
          (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:117" *)
          casez (ctl__req)
            /* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:117" */
            1'h1:
                \fsm_state$next  = 4'h1;
          endcase
        end
    endcase
    (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/amaranth/build/__editable__.amaranth-0.4.dev183+gfc85feb-py3-none-any/amaranth/hdl/xfrm.py:504" *)
    casez (rst)
      1'h1:
          \fsm_state$next  = 4'h0;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2184:dump_module$1 ) begin end
    efb__cyc = 1'h0;
    (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:161" *)
    casez (fsm_state)
      /* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:162" */
      /* \amaranth.decoding  = "IDLE/0" */
      4'h0:
          /* empty */;
      /* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:165" */
      /* \amaranth.decoding  = "WB_ENABLE_1/1" */
      4'h1:
          efb__cyc = 1'h1;
      /* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:174" */
      /* \amaranth.decoding  = "WB_ENABLE_2/2" */
      4'h2:
          /* empty */;
      /* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:179" */
      /* \amaranth.decoding  = "WB_CMD_1/3" */
      4'h3:
          efb__cyc = 1'h1;
      /* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:188" */
      /* \amaranth.decoding  = "WB_CMD_2/4" */
      4'h4:
          /* empty */;
      /* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:201" */
      /* \amaranth.decoding  = "WB_OPERAND_1/5" */
      4'h5:
          efb__cyc = 1'h1;
      /* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:208" */
      /* \amaranth.decoding  = "WB_OPERAND_2/8" */
      4'h8:
          /* empty */;
      /* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:224" */
      /* \amaranth.decoding  = "WB_DATA_1/6" */
      4'h6:
          (* full_case = 32'd1 *)
          (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:226" *)
          casez (ctl__xfer_is_wr)
            /* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:226" */
            1'h1:
                efb__cyc = 1'h1;
            /* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:229" */
            default:
                efb__cyc = 1'h1;
          endcase
      /* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:238" */
      /* \amaranth.decoding  = "WB_DATA_2/9" */
      4'h9:
          /* empty */;
      /* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:256" */
      /* \amaranth.decoding  = "WB_DISABLE_1/7" */
      4'h7:
          efb__cyc = 1'h1;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2184:dump_module$1 ) begin end
    ctl__done = 1'h0;
    (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:161" *)
    casez (fsm_state)
      /* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:162" */
      /* \amaranth.decoding  = "IDLE/0" */
      4'h0:
          /* empty */;
      /* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:165" */
      /* \amaranth.decoding  = "WB_ENABLE_1/1" */
      4'h1:
          /* empty */;
      /* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:174" */
      /* \amaranth.decoding  = "WB_ENABLE_2/2" */
      4'h2:
          /* empty */;
      /* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:179" */
      /* \amaranth.decoding  = "WB_CMD_1/3" */
      4'h3:
          /* empty */;
      /* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:188" */
      /* \amaranth.decoding  = "WB_CMD_2/4" */
      4'h4:
          /* empty */;
      /* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:201" */
      /* \amaranth.decoding  = "WB_OPERAND_1/5" */
      4'h5:
          /* empty */;
      /* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:208" */
      /* \amaranth.decoding  = "WB_OPERAND_2/8" */
      4'h8:
          /* empty */;
      /* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:224" */
      /* \amaranth.decoding  = "WB_DATA_1/6" */
      4'h6:
          /* empty */;
      /* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:238" */
      /* \amaranth.decoding  = "WB_DATA_2/9" */
      4'h9:
          /* empty */;
      /* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:256" */
      /* \amaranth.decoding  = "WB_DISABLE_1/7" */
      4'h7:
          /* empty */;
      /* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:262" */
      /* \amaranth.decoding  = "WB_DISABLE_2/10" */
      4'ha:
          ctl__done = 1'h1;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2184:dump_module$1 ) begin end
    efb__stb = 1'h0;
    (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:161" *)
    casez (fsm_state)
      /* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:162" */
      /* \amaranth.decoding  = "IDLE/0" */
      4'h0:
          /* empty */;
      /* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:165" */
      /* \amaranth.decoding  = "WB_ENABLE_1/1" */
      4'h1:
          efb__stb = 1'h1;
      /* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:174" */
      /* \amaranth.decoding  = "WB_ENABLE_2/2" */
      4'h2:
          /* empty */;
      /* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:179" */
      /* \amaranth.decoding  = "WB_CMD_1/3" */
      4'h3:
          efb__stb = 1'h1;
      /* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:188" */
      /* \amaranth.decoding  = "WB_CMD_2/4" */
      4'h4:
          /* empty */;
      /* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:201" */
      /* \amaranth.decoding  = "WB_OPERAND_1/5" */
      4'h5:
          efb__stb = 1'h1;
      /* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:208" */
      /* \amaranth.decoding  = "WB_OPERAND_2/8" */
      4'h8:
          /* empty */;
      /* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:224" */
      /* \amaranth.decoding  = "WB_DATA_1/6" */
      4'h6:
          (* full_case = 32'd1 *)
          (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:226" *)
          casez (ctl__xfer_is_wr)
            /* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:226" */
            1'h1:
                efb__stb = 1'h1;
            /* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:229" */
            default:
                efb__stb = 1'h1;
          endcase
      /* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:238" */
      /* \amaranth.decoding  = "WB_DATA_2/9" */
      4'h9:
          /* empty */;
      /* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:256" */
      /* \amaranth.decoding  = "WB_DISABLE_1/7" */
      4'h7:
          efb__stb = 1'h1;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2184:dump_module$1 ) begin end
    efb__we = 1'h0;
    (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:161" *)
    casez (fsm_state)
      /* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:162" */
      /* \amaranth.decoding  = "IDLE/0" */
      4'h0:
          /* empty */;
      /* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:165" */
      /* \amaranth.decoding  = "WB_ENABLE_1/1" */
      4'h1:
          efb__we = 1'h1;
      /* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:174" */
      /* \amaranth.decoding  = "WB_ENABLE_2/2" */
      4'h2:
          /* empty */;
      /* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:179" */
      /* \amaranth.decoding  = "WB_CMD_1/3" */
      4'h3:
          efb__we = 1'h1;
      /* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:188" */
      /* \amaranth.decoding  = "WB_CMD_2/4" */
      4'h4:
          /* empty */;
      /* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:201" */
      /* \amaranth.decoding  = "WB_OPERAND_1/5" */
      4'h5:
          efb__we = 1'h1;
      /* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:208" */
      /* \amaranth.decoding  = "WB_OPERAND_2/8" */
      4'h8:
          /* empty */;
      /* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:224" */
      /* \amaranth.decoding  = "WB_DATA_1/6" */
      4'h6:
          (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:226" *)
          casez (ctl__xfer_is_wr)
            /* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:226" */
            1'h1:
                efb__we = 1'h1;
          endcase
      /* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:238" */
      /* \amaranth.decoding  = "WB_DATA_2/9" */
      4'h9:
          /* empty */;
      /* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:256" */
      /* \amaranth.decoding  = "WB_DISABLE_1/7" */
      4'h7:
          efb__we = 1'h1;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2184:dump_module$1 ) begin end
    efb__dat_w = 8'h00;
    (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:161" *)
    casez (fsm_state)
      /* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:162" */
      /* \amaranth.decoding  = "IDLE/0" */
      4'h0:
          /* empty */;
      /* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:165" */
      /* \amaranth.decoding  = "WB_ENABLE_1/1" */
      4'h1:
          efb__dat_w = 8'h80;
      /* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:174" */
      /* \amaranth.decoding  = "WB_ENABLE_2/2" */
      4'h2:
          /* empty */;
      /* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:179" */
      /* \amaranth.decoding  = "WB_CMD_1/3" */
      4'h3:
          efb__dat_w = ctl__cmd[7:0];
      /* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:188" */
      /* \amaranth.decoding  = "WB_CMD_2/4" */
      4'h4:
          efb__dat_w = ctl__cmd[7:0];
      /* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:201" */
      /* \amaranth.decoding  = "WB_OPERAND_1/5" */
      4'h5:
          (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:136" *)
          casez (curr_op)
            /* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:137" */
            2'h0:
                efb__dat_w = ctl__cmd[31:24];
            /* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:139" */
            2'h1:
                efb__dat_w = ctl__cmd[23:16];
            /* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:141" */
            2'h2:
                efb__dat_w = ctl__cmd[15:8];
          endcase
      /* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:208" */
      /* \amaranth.decoding  = "WB_OPERAND_2/8" */
      4'h8:
          (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:136" *)
          casez (curr_op)
            /* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:137" */
            2'h0:
                efb__dat_w = ctl__cmd[31:24];
            /* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:139" */
            2'h1:
                efb__dat_w = ctl__cmd[23:16];
            /* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:141" */
            2'h2:
                efb__dat_w = ctl__cmd[15:8];
          endcase
      /* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:224" */
      /* \amaranth.decoding  = "WB_DATA_1/6" */
      4'h6:
          (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:149" *)
          casez (curr_data)
            /* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:150" */
            6'h00:
                efb__dat_w = ctl__wr__data[31:24];
            /* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:152" */
            6'h01:
                efb__dat_w = ctl__wr__data[23:16];
            /* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:154" */
            6'h02:
                efb__dat_w = ctl__wr__data[15:8];
            /* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:156" */
            6'h03:
                efb__dat_w = ctl__wr__data[7:0];
          endcase
      /* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:238" */
      /* \amaranth.decoding  = "WB_DATA_2/9" */
      4'h9:
          (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:149" *)
          casez (curr_data)
            /* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:150" */
            6'h00:
                efb__dat_w = ctl__wr__data[31:24];
            /* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:152" */
            6'h01:
                efb__dat_w = ctl__wr__data[23:16];
            /* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:154" */
            6'h02:
                efb__dat_w = ctl__wr__data[15:8];
            /* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:156" */
            6'h03:
                efb__dat_w = ctl__wr__data[7:0];
          endcase
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2184:dump_module$1 ) begin end
    efb__adr = 8'h00;
    (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:161" *)
    casez (fsm_state)
      /* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:162" */
      /* \amaranth.decoding  = "IDLE/0" */
      4'h0:
          /* empty */;
      /* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:165" */
      /* \amaranth.decoding  = "WB_ENABLE_1/1" */
      4'h1:
          efb__adr = 8'h70;
      /* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:174" */
      /* \amaranth.decoding  = "WB_ENABLE_2/2" */
      4'h2:
          efb__adr = 8'h70;
      /* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:179" */
      /* \amaranth.decoding  = "WB_CMD_1/3" */
      4'h3:
          efb__adr = 8'h71;
      /* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:188" */
      /* \amaranth.decoding  = "WB_CMD_2/4" */
      4'h4:
          efb__adr = 8'h71;
      /* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:201" */
      /* \amaranth.decoding  = "WB_OPERAND_1/5" */
      4'h5:
          efb__adr = 8'h71;
      /* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:208" */
      /* \amaranth.decoding  = "WB_OPERAND_2/8" */
      4'h8:
          efb__adr = 8'h71;
      /* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:224" */
      /* \amaranth.decoding  = "WB_DATA_1/6" */
      4'h6:
          (* full_case = 32'd1 *)
          (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:226" *)
          casez (ctl__xfer_is_wr)
            /* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:226" */
            1'h1:
                efb__adr = 8'h71;
            /* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:229" */
            default:
                efb__adr = 8'h73;
          endcase
      /* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:238" */
      /* \amaranth.decoding  = "WB_DATA_2/9" */
      4'h9:
          (* full_case = 32'd1 *)
          (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:240" *)
          casez (ctl__xfer_is_wr)
            /* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:240" */
            1'h1:
                efb__adr = 8'h71;
            /* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:242" */
            default:
                efb__adr = 8'h73;
          endcase
      /* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:256" */
      /* \amaranth.decoding  = "WB_DISABLE_1/7" */
      4'h7:
          efb__adr = 8'h70;
      /* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:262" */
      /* \amaranth.decoding  = "WB_DISABLE_2/10" */
      4'ha:
          efb__adr = 8'h70;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2184:dump_module$1 ) begin end
    \curr_op$next  = curr_op;
    (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:161" *)
    casez (fsm_state)
      /* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:162" */
      /* \amaranth.decoding  = "IDLE/0" */
      4'h0:
          /* empty */;
      /* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:165" */
      /* \amaranth.decoding  = "WB_ENABLE_1/1" */
      4'h1:
          /* empty */;
      /* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:174" */
      /* \amaranth.decoding  = "WB_ENABLE_2/2" */
      4'h2:
          /* empty */;
      /* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:179" */
      /* \amaranth.decoding  = "WB_CMD_1/3" */
      4'h3:
          /* empty */;
      /* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:188" */
      /* \amaranth.decoding  = "WB_CMD_2/4" */
      4'h4:
          /* empty */;
      /* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:201" */
      /* \amaranth.decoding  = "WB_OPERAND_1/5" */
      4'h5:
          /* empty */;
      /* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:208" */
      /* \amaranth.decoding  = "WB_OPERAND_2/8" */
      4'h8:
          (* full_case = 32'd1 *)
          (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:212" *)
          casez (\$23 )
            /* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:212" */
            1'h1:
                \curr_op$next  = \$26 [1:0];
            /* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:214" */
            default:
                \curr_op$next  = 2'h0;
          endcase
    endcase
    (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/amaranth/build/__editable__.amaranth-0.4.dev183+gfc85feb-py3-none-any/amaranth/hdl/xfrm.py:504" *)
    casez (rst)
      1'h1:
          \curr_op$next  = 2'h0;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2184:dump_module$1 ) begin end
    \ctl__rd__data$next  = ctl__rd__data;
    (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:161" *)
    casez (fsm_state)
      /* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:162" */
      /* \amaranth.decoding  = "IDLE/0" */
      4'h0:
          /* empty */;
      /* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:165" */
      /* \amaranth.decoding  = "WB_ENABLE_1/1" */
      4'h1:
          /* empty */;
      /* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:174" */
      /* \amaranth.decoding  = "WB_ENABLE_2/2" */
      4'h2:
          /* empty */;
      /* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:179" */
      /* \amaranth.decoding  = "WB_CMD_1/3" */
      4'h3:
          /* empty */;
      /* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:188" */
      /* \amaranth.decoding  = "WB_CMD_2/4" */
      4'h4:
          /* empty */;
      /* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:201" */
      /* \amaranth.decoding  = "WB_OPERAND_1/5" */
      4'h5:
          /* empty */;
      /* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:208" */
      /* \amaranth.decoding  = "WB_OPERAND_2/8" */
      4'h8:
          /* empty */;
      /* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:224" */
      /* \amaranth.decoding  = "WB_DATA_1/6" */
      4'h6:
          (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:233" *)
          casez (efb__ack)
            /* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:233" */
            1'h1:
                \ctl__rd__data$next  = efb__dat_r;
          endcase
    endcase
    (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/amaranth/build/__editable__.amaranth-0.4.dev183+gfc85feb-py3-none-any/amaranth/hdl/xfrm.py:504" *)
    casez (rst)
      1'h1:
          \ctl__rd__data$next  = 8'h00;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2184:dump_module$1 ) begin end
    ctl__rd__stb = 1'h0;
    (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:161" *)
    casez (fsm_state)
      /* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:162" */
      /* \amaranth.decoding  = "IDLE/0" */
      4'h0:
          /* empty */;
      /* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:165" */
      /* \amaranth.decoding  = "WB_ENABLE_1/1" */
      4'h1:
          /* empty */;
      /* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:174" */
      /* \amaranth.decoding  = "WB_ENABLE_2/2" */
      4'h2:
          /* empty */;
      /* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:179" */
      /* \amaranth.decoding  = "WB_CMD_1/3" */
      4'h3:
          /* empty */;
      /* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:188" */
      /* \amaranth.decoding  = "WB_CMD_2/4" */
      4'h4:
          /* empty */;
      /* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:201" */
      /* \amaranth.decoding  = "WB_OPERAND_1/5" */
      4'h5:
          /* empty */;
      /* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:208" */
      /* \amaranth.decoding  = "WB_OPERAND_2/8" */
      4'h8:
          /* empty */;
      /* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:224" */
      /* \amaranth.decoding  = "WB_DATA_1/6" */
      4'h6:
          /* empty */;
      /* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:238" */
      /* \amaranth.decoding  = "WB_DATA_2/9" */
      4'h9:
          ctl__rd__stb = 1'h1;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2184:dump_module$1 ) begin end
    \curr_data$next  = curr_data;
    (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:161" *)
    casez (fsm_state)
      /* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:162" */
      /* \amaranth.decoding  = "IDLE/0" */
      4'h0:
          /* empty */;
      /* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:165" */
      /* \amaranth.decoding  = "WB_ENABLE_1/1" */
      4'h1:
          /* empty */;
      /* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:174" */
      /* \amaranth.decoding  = "WB_ENABLE_2/2" */
      4'h2:
          /* empty */;
      /* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:179" */
      /* \amaranth.decoding  = "WB_CMD_1/3" */
      4'h3:
          /* empty */;
      /* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:188" */
      /* \amaranth.decoding  = "WB_CMD_2/4" */
      4'h4:
          /* empty */;
      /* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:201" */
      /* \amaranth.decoding  = "WB_OPERAND_1/5" */
      4'h5:
          /* empty */;
      /* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:208" */
      /* \amaranth.decoding  = "WB_OPERAND_2/8" */
      4'h8:
          /* empty */;
      /* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:224" */
      /* \amaranth.decoding  = "WB_DATA_1/6" */
      4'h6:
          /* empty */;
      /* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:238" */
      /* \amaranth.decoding  = "WB_DATA_2/9" */
      4'h9:
          (* full_case = 32'd1 *)
          (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:246" *)
          casez (\$32 )
            /* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:246" */
            1'h1:
                \curr_data$next  = \$35 [5:0];
            /* src = "C:/msys64/home/William/Projects/FPGA/amaranth/efbutils/ufm_reader/ufm_reader/sequencer.py:248" */
            default:
                \curr_data$next  = 6'h00;
          endcase
    endcase
    (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/amaranth/build/__editable__.amaranth-0.4.dev183+gfc85feb-py3-none-any/amaranth/hdl/xfrm.py:504" *)
    casez (rst)
      1'h1:
          \curr_data$next  = 6'h00;
    endcase
  end
  assign \$25  = \$26 ;
  assign \$34  = \$35 ;
endmodule

(* \amaranth.hierarchy  = "sequencer" *)
(* top =  1  *)
(* generator = "Amaranth" *)
module sequencer(ctl__data_len, ctl__done, ctl__op_len, ctl__req, ctl__xfer_is_wr, efb__ack, efb__adr, efb__cyc, efb__dat_r, efb__dat_w, efb__stb, efb__we, rd__data, rd__stb, wr__ready, wr__valid, clk, rst, ctl__cmd__cmd);
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/amaranth/build/__editable__.amaranth-0.4.dev183+gfc85feb-py3-none-any/amaranth/lib/wiring.py:227" *)
  wire [31:0] \U$$0_ctl__cmd ;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/amaranth/build/__editable__.amaranth-0.4.dev183+gfc85feb-py3-none-any/amaranth/lib/wiring.py:227" *)
  wire [5:0] \U$$0_ctl__data_len ;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/amaranth/build/__editable__.amaranth-0.4.dev183+gfc85feb-py3-none-any/amaranth/lib/wiring.py:227" *)
  wire \U$$0_ctl__done ;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/amaranth/build/__editable__.amaranth-0.4.dev183+gfc85feb-py3-none-any/amaranth/lib/wiring.py:227" *)
  wire [1:0] \U$$0_ctl__op_len ;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/amaranth/build/__editable__.amaranth-0.4.dev183+gfc85feb-py3-none-any/amaranth/lib/wiring.py:227" *)
  wire [7:0] \U$$0_ctl__rd__data ;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/amaranth/build/__editable__.amaranth-0.4.dev183+gfc85feb-py3-none-any/amaranth/lib/wiring.py:227" *)
  wire \U$$0_ctl__rd__stb ;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/amaranth/build/__editable__.amaranth-0.4.dev183+gfc85feb-py3-none-any/amaranth/lib/wiring.py:227" *)
  wire \U$$0_ctl__req ;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/amaranth/build/__editable__.amaranth-0.4.dev183+gfc85feb-py3-none-any/amaranth/lib/wiring.py:227" *)
  wire [31:0] \U$$0_ctl__wr__data ;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/amaranth/build/__editable__.amaranth-0.4.dev183+gfc85feb-py3-none-any/amaranth/lib/wiring.py:227" *)
  wire \U$$0_ctl__xfer_is_wr ;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/amaranth/build/__editable__.amaranth-0.4.dev183+gfc85feb-py3-none-any/amaranth/lib/wiring.py:227" *)
  wire \U$$0_efb__ack ;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/amaranth/build/__editable__.amaranth-0.4.dev183+gfc85feb-py3-none-any/amaranth/lib/wiring.py:227" *)
  wire [7:0] \U$$0_efb__adr ;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/amaranth/build/__editable__.amaranth-0.4.dev183+gfc85feb-py3-none-any/amaranth/lib/wiring.py:227" *)
  wire \U$$0_efb__cyc ;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/amaranth/build/__editable__.amaranth-0.4.dev183+gfc85feb-py3-none-any/amaranth/lib/wiring.py:227" *)
  wire [7:0] \U$$0_efb__dat_r ;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/amaranth/build/__editable__.amaranth-0.4.dev183+gfc85feb-py3-none-any/amaranth/lib/wiring.py:227" *)
  wire [7:0] \U$$0_efb__dat_w ;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/amaranth/build/__editable__.amaranth-0.4.dev183+gfc85feb-py3-none-any/amaranth/lib/wiring.py:227" *)
  wire \U$$0_efb__stb ;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/amaranth/build/__editable__.amaranth-0.4.dev183+gfc85feb-py3-none-any/amaranth/lib/wiring.py:227" *)
  wire \U$$0_efb__we ;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/amaranth/build/__editable__.amaranth-0.4.dev183+gfc85feb-py3-none-any/amaranth/hdl/ir.py:532" *)
  input clk;
  wire clk;
  (* enum_base_type = "Name" *)
  (* enum_value_00000000 = "IDLE" *)
  (* enum_value_00100110 = "DISABLE_CONFIG" *)
  (* enum_value_00111100 = "POLL_STATUS" *)
  (* enum_value_01110100 = "ENABLE_CONFIG" *)
  (* enum_value_10110100 = "SET_UFM_ADDR" *)
  (* enum_value_11001010 = "READ_UFM" *)
  (* enum_value_11111111 = "BYPASS" *)
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/amaranth/build/__editable__.amaranth-0.4.dev183+gfc85feb-py3-none-any/amaranth/lib/wiring.py:227" *)
  input [7:0] ctl__cmd__cmd;
  wire [7:0] ctl__cmd__cmd;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/amaranth/build/__editable__.amaranth-0.4.dev183+gfc85feb-py3-none-any/amaranth/lib/wiring.py:227" *)
  wire [23:0] ctl__cmd__ops;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/amaranth/build/__editable__.amaranth-0.4.dev183+gfc85feb-py3-none-any/amaranth/lib/wiring.py:227" *)
  input [5:0] ctl__data_len;
  wire [5:0] ctl__data_len;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/amaranth/build/__editable__.amaranth-0.4.dev183+gfc85feb-py3-none-any/amaranth/lib/wiring.py:227" *)
  output ctl__done;
  wire ctl__done;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/amaranth/build/__editable__.amaranth-0.4.dev183+gfc85feb-py3-none-any/amaranth/lib/wiring.py:227" *)
  input [1:0] ctl__op_len;
  wire [1:0] ctl__op_len;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/amaranth/build/__editable__.amaranth-0.4.dev183+gfc85feb-py3-none-any/amaranth/lib/wiring.py:227" *)
  input ctl__req;
  wire ctl__req;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/amaranth/build/__editable__.amaranth-0.4.dev183+gfc85feb-py3-none-any/amaranth/lib/wiring.py:227" *)
  wire ctl__wr__ready;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/amaranth/build/__editable__.amaranth-0.4.dev183+gfc85feb-py3-none-any/amaranth/lib/wiring.py:227" *)
  wire ctl__wr__valid;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/amaranth/build/__editable__.amaranth-0.4.dev183+gfc85feb-py3-none-any/amaranth/lib/wiring.py:227" *)
  input ctl__xfer_is_wr;
  wire ctl__xfer_is_wr;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/amaranth/build/__editable__.amaranth-0.4.dev183+gfc85feb-py3-none-any/amaranth/lib/wiring.py:227" *)
  input efb__ack;
  wire efb__ack;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/amaranth/build/__editable__.amaranth-0.4.dev183+gfc85feb-py3-none-any/amaranth/lib/wiring.py:227" *)
  output [7:0] efb__adr;
  wire [7:0] efb__adr;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/amaranth/build/__editable__.amaranth-0.4.dev183+gfc85feb-py3-none-any/amaranth/lib/wiring.py:227" *)
  output efb__cyc;
  wire efb__cyc;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/amaranth/build/__editable__.amaranth-0.4.dev183+gfc85feb-py3-none-any/amaranth/lib/wiring.py:227" *)
  input [7:0] efb__dat_r;
  wire [7:0] efb__dat_r;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/amaranth/build/__editable__.amaranth-0.4.dev183+gfc85feb-py3-none-any/amaranth/lib/wiring.py:227" *)
  output [7:0] efb__dat_w;
  wire [7:0] efb__dat_w;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/amaranth/build/__editable__.amaranth-0.4.dev183+gfc85feb-py3-none-any/amaranth/lib/wiring.py:227" *)
  output efb__stb;
  wire efb__stb;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/amaranth/build/__editable__.amaranth-0.4.dev183+gfc85feb-py3-none-any/amaranth/lib/wiring.py:227" *)
  output efb__we;
  wire efb__we;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/amaranth/build/__editable__.amaranth-0.4.dev183+gfc85feb-py3-none-any/amaranth/lib/wiring.py:227" *)
  output [7:0] rd__data;
  wire [7:0] rd__data;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/amaranth/build/__editable__.amaranth-0.4.dev183+gfc85feb-py3-none-any/amaranth/lib/wiring.py:227" *)
  output rd__stb;
  wire rd__stb;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/amaranth/build/__editable__.amaranth-0.4.dev183+gfc85feb-py3-none-any/amaranth/hdl/ir.py:532" *)
  input rst;
  wire rst;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/amaranth/build/__editable__.amaranth-0.4.dev183+gfc85feb-py3-none-any/amaranth/lib/wiring.py:227" *)
  wire [31:0] wr__data;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/amaranth/build/__editable__.amaranth-0.4.dev183+gfc85feb-py3-none-any/amaranth/lib/wiring.py:227" *)
  output wr__ready;
  wire wr__ready;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/amaranth/build/__editable__.amaranth-0.4.dev183+gfc85feb-py3-none-any/amaranth/lib/wiring.py:227" *)
  input wr__valid;
  wire wr__valid;
  \U$$0  \U$$0  (
    .clk(clk),
    .ctl__cmd(\U$$0_ctl__cmd ),
    .ctl__data_len(\U$$0_ctl__data_len ),
    .ctl__done(\U$$0_ctl__done ),
    .ctl__op_len(\U$$0_ctl__op_len ),
    .ctl__rd__data(\U$$0_ctl__rd__data ),
    .ctl__rd__stb(\U$$0_ctl__rd__stb ),
    .ctl__req(\U$$0_ctl__req ),
    .ctl__wr__data(32'd0),
    .ctl__xfer_is_wr(\U$$0_ctl__xfer_is_wr ),
    .efb__ack(\U$$0_efb__ack ),
    .efb__adr(\U$$0_efb__adr ),
    .efb__cyc(\U$$0_efb__cyc ),
    .efb__dat_r(\U$$0_efb__dat_r ),
    .efb__dat_w(\U$$0_efb__dat_w ),
    .efb__stb(\U$$0_efb__stb ),
    .efb__we(\U$$0_efb__we ),
    .rst(rst)
  );
  assign wr__data = 32'd0;
  assign ctl__wr__ready = 1'h0;
  assign ctl__cmd__ops = 24'h000000;
  assign \U$$0_ctl__xfer_is_wr  = ctl__xfer_is_wr;
  assign \U$$0_ctl__data_len  = ctl__data_len;
  assign \U$$0_ctl__op_len  = ctl__op_len;
  assign ctl__done = \U$$0_ctl__done ;
  assign \U$$0_ctl__cmd [31:8] = 24'h000000;
  assign \U$$0_ctl__cmd [7:0] = ctl__cmd__cmd;
  assign \U$$0_ctl__req  = ctl__req;
  assign efb__we = \U$$0_efb__we ;
  assign efb__stb = \U$$0_efb__stb ;
  assign efb__dat_w = \U$$0_efb__dat_w ;
  assign \U$$0_efb__dat_r  = efb__dat_r;
  assign efb__cyc = \U$$0_efb__cyc ;
  assign efb__adr = \U$$0_efb__adr ;
  assign \U$$0_efb__ack  = efb__ack;
  assign rd__stb = \U$$0_ctl__rd__stb ;
  assign rd__data = \U$$0_ctl__rd__data ;
  assign ctl__wr__valid = wr__valid;
  assign wr__ready = 1'h0;
  assign \U$$0_ctl__wr__data  = 32'd0;
endmodule