William@DESKTOP-3H1DSBV MINGW64 ~/Projects/FPGA/amaranth/smolarith
$ yosys -p 'bugpoint -command "synth_ice40"' b2tob1000.v

 /----------------------------------------------------------------------------\
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |  Copyright (C) 2012 - 2024  Claire Xenia Wolf <claire@yosyshq.com>         |
 |  Distributed under an ISC-like license, type "license" to see terms        |
 \----------------------------------------------------------------------------/
 Yosys 0.40+25 (git sha1 171577f90, sccache x86_64-w64-mingw32-g++ 13.2.0 -Os)

-- Parsing `b2tob1000.v' using frontend ` -vlog2k' --

1. Executing Verilog-2005 frontend: b2tob1000.v
Parsing Verilog input from `b2tob1000.v' to AST representation.
Storing AST representation for module `$abstract\top'.
Successfully finished Verilog frontend.

-- Running command `bugpoint -command "synth_ice40"' --

2. Executing BUGPOINT pass (minimize testcases).
ERROR: Module `$abstract\top' is used with parameters but is not parametric!

2.1. Trying to remove module $abstract\top.
Testcase does not crash.
Demoting introduced module ports.

2.2. Trying to remove module $abstract\top.
Testcase does not crash.
Simplifications exhausted.

End of script. Logfile hash: 7a496ecfb0
Yosys 0.40+25 (git sha1 171577f90, sccache x86_64-w64-mingw32-g++ 13.2.0 -Os)
Time spent: 33% 2x read_verilog (0 sec), 33% 1x read (0 sec), ...