diff --git a/core/stellar.py b/core/stellar.py index 1923805..5657d76 100644 --- a/core/stellar.py +++ b/core/stellar.py @@ -19,6 +19,7 @@ from . import lxbuildenv from migen import * from migen.genlib.resetsync import AsyncResetSynchronizer +from litex.build.generic_platform import * from litex.build.io import DDROutput from litex.soc.cores.clock.gowin_gw1n import GW1NPLL @@ -146,7 +147,8 @@ class BaseSoC(SoCCore): self.add_sdram("sdram", phy = self.sdrphy, module = MT48LC4M16(sys_clk_freq, sdram_rate), # FIXME. - l2_cache_size = 0, + l2_cache_size = 1024, + l2_cache_min_data_width = 32 ) # SPIBone ---------------------------------------------------------------------------------- @@ -158,6 +160,30 @@ class BaseSoC(SoCCore): self.submodules.lpcbone = LPCBone(platform, lpc_pads) self.add_wb_master(self.lpcbone.bus) + self.platform.add_extension([("sdram_wb", 0, + Subsignal("cyc", Pins("fpc:0")), + Subsignal("stb", Pins("fpc:1")), + Subsignal("ack", Pins("fpc:2")), + Subsignal("lpcbone_cyc", Pins("fpc:3")), + Subsignal("lpcbone_stb", Pins("fpc:4")), + Subsignal("lpcbone_ack", Pins("fpc:5")), + IOStandard("LVCMOS33") + )]) + + wb_sdram = self.bus.slaves["main_ram"] + breakout = platform.request("sdram_wb") + + print(dir(breakout)) + + self.comb += [ + breakout.cyc.eq(wb_sdram.cyc), + breakout.stb.eq(wb_sdram.stb), + breakout.ack.eq(wb_sdram.ack), + breakout.lpcbone_cyc.eq(self.lpcbone.bus.cyc), + breakout.lpcbone_stb.eq(self.lpcbone.bus.stb), + breakout.lpcbone_ack.eq(self.lpcbone.bus.ack), + ] + # Build -------------------------------------------------------------------------------------------- def main(): # The LiteX SoC and FPGA build flow is VERY customizable out-of-the-box.