William@DESKTOP-3H1DSBV MINGW64 /c/msys64/home/William/Projects/FPGA/amaranth/efbutils
$ yosys -qp 'read_verilog << EOF'
module my_task();
    task foo(input a);
        begin
            a = 1;
        end
    endtask

    wire bar;
    foo(bar);
endmodule
EOF
<stdin>:9: ERROR: syntax error, unexpected '(', expecting TOK_ID or '#'