/* Generated by Yosys 0.40+25 (git sha1 171577f90, sccache x86_64-w64-mingw32-g++ 13.2.0 -Os) */

(* top =  1  *)
(* src = "C:/msys64/home/William/Projects/FPGA/amaranth/smolarith/src/smolarith/base10.py:347" *)
(* generator = "Amaranth" *)
module top(inp__valid, outp__ready, clk, rst, inp__ready, outp__payload, outp__valid, inp__payload);
  reg \$auto$verilog_backend.cc:2352:dump_module$1  = 0;
  wire \$1 ;
  wire [11:0] \$10 ;
  wire [10:0] \$11 ;
  reg [1:0] \$12 ;
  reg [9:0] \$13 ;
  reg [14:0] \$14 ;
  reg [10:0] \$15 ;
  reg [9:0] \$16 ;
  reg \$17 ;
  reg [19:0] \$18 ;
  wire \$2 ;
  wire \$3 ;
  wire [14:0] \$4 ;
  wire [15:0] \$5 ;
  wire [9:0] \$6 ;
  wire [10:0] \$7 ;
  wire [10:0] \$8 ;
  wire \$9 ;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/smolarith/src/smolarith/base10.py:349" *)
  reg [9:0] b2 = 10'h000;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/smolarith/src/smolarith/base10.py:350" *)
  reg [14:0] c = 15'h0000;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/smolarith/.venv/lib/python3.11/site-packages/amaranth/hdl/_ir.py:270" *)
  input clk;
  wire clk;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/smolarith/src/smolarith/base10.py:351" *)
  reg [10:0] d0_guess = 11'h000;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/smolarith/src/smolarith/base10.py:352" *)
  reg [9:0] d1_guess = 10'h000;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/smolarith/src/smolarith/base10.py:202" *)
  input [19:0] inp__payload;
  wire [19:0] inp__payload;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/smolarith/src/smolarith/base10.py:355" *)
  output inp__ready;
  reg inp__ready;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/smolarith/src/smolarith/base10.py:204" *)
  input inp__valid;
  wire inp__valid;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/smolarith/src/smolarith/base10.py:355" *)
  wire not_stalled;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/smolarith/src/smolarith/base10.py:333" *)
  output [19:0] outp__payload;
  reg [19:0] outp__payload = 20'h00000;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/smolarith/src/smolarith/base10.py:333" *)
  wire [9:0] \outp__payload[0] ;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/smolarith/src/smolarith/base10.py:333" *)
  wire [9:0] \outp__payload[1] ;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/smolarith/src/smolarith/base10.py:260" *)
  input outp__ready;
  wire outp__ready;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/smolarith/src/smolarith/base10.py:261" *)
  output outp__valid;
  reg outp__valid = 1'h0;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/smolarith/.venv/lib/python3.11/site-packages/amaranth/hdl/_ir.py:270" *)
  input rst;
  wire rst;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/smolarith/src/smolarith/base10.py:354" *)
  reg [1:0] valid = 2'h0;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/smolarith/src/smolarith/base10.py:354" *)
  wire \valid[0] ;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/smolarith/src/smolarith/base10.py:354" *)
  wire \valid[1] ;
  assign \$1  = ~ (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/smolarith/src/smolarith/base10.py:357" *) outp__valid;
  assign \$2  = \$1  | (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/smolarith/src/smolarith/base10.py:357" *) outp__ready;
  assign \$3  = inp__ready & (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/smolarith/src/smolarith/base10.py:362" *) inp__valid;
  assign \$4  = 5'h18 * (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/smolarith/src/smolarith/base10.py:323" *) inp__payload[19:10];
  assign \$5  = \$4  + (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/smolarith/src/smolarith/base10.py:323" *) inp__payload[9:0];
  assign \$6  = 5'h18 * (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/smolarith/src/smolarith/base10.py:323" *) c[14:10];
  assign \$7  = \$6  + (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/smolarith/src/smolarith/base10.py:323" *) c[9:0];
  assign \$8  = b2 + (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/smolarith/src/smolarith/base10.py:372" *) c[14:10];
  assign \$9  = d0_guess > (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/smolarith/src/smolarith/base10.py:378" *) 10'h3e7;
  assign \$10  = d0_guess + (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/smolarith/src/smolarith/base10.py:380" *) 5'h18;
  assign \$11  = d1_guess + (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/smolarith/src/smolarith/base10.py:381" *) 1'h1;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/smolarith/src/smolarith/base10.py:354" *)
  always @(posedge clk)
    valid <= \$12 ;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/smolarith/src/smolarith/base10.py:349" *)
  always @(posedge clk)
    b2 <= \$13 ;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/smolarith/src/smolarith/base10.py:350" *)
  always @(posedge clk)
    c <= \$14 ;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/smolarith/src/smolarith/base10.py:351" *)
  always @(posedge clk)
    d0_guess <= \$15 ;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/smolarith/src/smolarith/base10.py:352" *)
  always @(posedge clk)
    d1_guess <= \$16 ;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/smolarith/src/smolarith/base10.py:261" *)
  always @(posedge clk)
    outp__valid <= \$17 ;
  (* src = "C:/msys64/home/William/Projects/FPGA/amaranth/smolarith/src/smolarith/base10.py:333" *)
  always @(posedge clk)
    outp__payload <= \$18 ;
  always @* begin
    if (\$auto$verilog_backend.cc:2352:dump_module$1 ) begin end
    inp__ready = 1'h0;
    if (\$2 ) begin
      inp__ready = 1'h1;
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2352:dump_module$1 ) begin end
    \$12 [1] = valid[1];
    \$12 [0] = 1'h0;
    if (\$3 ) begin
      \$12 [0] = 1'h1;
    end
    if (inp__ready) begin
      \$12 [1] = valid[0];
    end
    if (rst) begin
      \$12  = 2'h0;
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2352:dump_module$1 ) begin end
    \$13  = b2;
    if (\$3 ) begin
      \$13  = inp__payload[19:10];
    end
    if (rst) begin
      \$13  = 10'h000;
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2352:dump_module$1 ) begin end
    \$14  = c;
    if (\$3 ) begin
      \$14  = \$5 [14:0];
    end
    if (rst) begin
      \$14  = 15'h0000;
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2352:dump_module$1 ) begin end
    \$15  = d0_guess;
    if (inp__ready) begin
      \$15  = \$7 ;
    end
    if (rst) begin
      \$15  = 11'h000;
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2352:dump_module$1 ) begin end
    \$16  = d1_guess;
    if (inp__ready) begin
      \$16  = \$8 [9:0];
    end
    if (rst) begin
      \$16  = 10'h000;
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2352:dump_module$1 ) begin end
    \$17  = outp__valid;
    if (inp__ready) begin
      \$17  = valid[1];
    end
    if (rst) begin
      \$17  = 1'h0;
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2352:dump_module$1 ) begin end
    \$18  = outp__payload;
    if (inp__ready) begin
      (* full_case = 32'd1 *)
      if (\$9 ) begin
        \$18 [9:0] = \$10 [9:0];
        \$18 [19:10] = \$11 [9:0];
      end else begin
        \$18 [9:0] = d0_guess[9:0];
        \$18 [19:10] = d1_guess;
      end
    end
    if (rst) begin
      \$18  = 20'h00000;
    end
  end
  assign not_stalled = inp__ready;
  assign \outp__payload[0]  = outp__payload[9:0];
  assign \outp__payload[1]  = outp__payload[19:10];
  assign \valid[0]  = valid[0];
  assign \valid[1]  = valid[1];
endmodule