diff --git a/examples/attosoc.py b/examples/attosoc.py
index 64ea6c7..fe07168 100644
--- a/examples/attosoc.py
+++ b/examples/attosoc.py
@@ -96,7 +96,8 @@ class Leds(Component):
         return self._signature
 
     def __init__(self):
-        self.mux = csr.bus.Multiplexer(addr_width=2, data_width=8, name="gpio")
+        self.mux = csr.bus.Multiplexer(addr_width=21, data_width=8,
+                                       alignment=2, name="gpio")
         self._signature = self.mux.signature
         self._signature.members += {
             "leds": Out(8),
@@ -146,6 +147,7 @@ class Timer(Component):
 
     def __init__(self):
         self.mux = csr.bus.Multiplexer(addr_width=1, data_width=8,
+                                       alignment=1,
                                        name="timer")
         self._signature = self.mux.signature
         self._signature.members += {
@@ -272,7 +274,8 @@ class WBSerial(Component):
         return self._signature
 
     def __init__(self):
-        self.mux = csr.bus.Multiplexer(addr_width=1, data_width=8,
+        self.mux = csr.bus.Multiplexer(addr_width=3, data_width=8,
+                                       alignment=2,
                                        name="serial")
         self._signature = self.mux.signature
         self._signature.members += {
@@ -374,7 +377,7 @@ class AttoSoC(Elaboratable):
         m = Module()
 
         # CSR (has to be done first other mem map "frozen" errors?)
-        periph_bus = csr.Decoder(addr_width=25, data_width=8, alignment=23,
+        periph_bus = csr.Decoder(addr_width=23, data_width=8, alignment=21,
                                  name="periph")
         periph_bus.add(self.leds.bus)
         if not self.sim:
@@ -382,9 +385,9 @@ class AttoSoC(Elaboratable):
             periph_bus.add(self.serial.bus)
 
         # Wishbone
-        periph_wb = WishboneCSRBridge(periph_bus.bus, data_width=32)
+        periph_wb = WishboneCSRBridge(periph_bus.bus, data_width=8)
         self.decoder.add(flipped(self.mem.bus))
-        self.decoder.add(flipped(periph_wb.wb_bus))
+        self.decoder.add(flipped(periph_wb.wb_bus), sparse=True)
 
         m.submodules.cpu = self.cpu
         m.submodules.mem = self.mem
@@ -478,6 +481,7 @@ def demo(args):
             j       next_int
     write_io:
             sw      s0,0(s1)
+            sw      s0,0xc(s1)
             call    delay
     not_prime:
             j       outer
diff --git a/sentinel-rt/examples/attosoc.rs b/sentinel-rt/examples/attosoc.rs
index f30dad9..c2764cf 100644
--- a/sentinel-rt/examples/attosoc.rs
+++ b/sentinel-rt/examples/attosoc.rs
@@ -29,7 +29,7 @@ fn read_timer_int(_cs: CriticalSection) -> u8 {
 }
 
 fn read_serial_int(_cs: CriticalSection) -> u8 {
-    unsafe { read_volatile(0x03000001 as *const u8) }
+    unsafe { read_volatile(0x03000010 as *const u8) }
 }
 
 fn read_serial_rx(_cs: CriticalSection) -> u8 {
@@ -41,7 +41,7 @@ fn write_serial_tx(_cs: CriticalSection, val: u8) {
 }
 
 fn read_inp_port(_cs: CriticalSection,) -> u8 {
-    unsafe { read_volatile(0x02000001 as *const u8) }
+    unsafe { read_volatile(0x02000004 as *const u8) }
 }
 
 fn write_leds(_cs: CriticalSection, val: u8) {
diff --git a/tests/sim/test_top.py b/tests/sim/test_top.py
index 4196b20..2e9de87 100644
--- a/tests/sim/test_top.py
+++ b/tests/sim/test_top.py
@@ -329,6 +329,7 @@ next_int:
         j       next_int
 write_io:
         sw      s0,0(s1)
+        sw      s0,0xc(s1)
         call    delay
 not_prime:
         j       outer