Synthesis Messages

Report Title GowinSynthesis Report
Design File C:\msys64\home\William\Projects\consult\MakeMHz\stellar-core\build\stellar_board\gateware\stellar_board.v
GowinSynthesis Constraints File ---
Version GowinSynthesis V1.9.8.06
Part Number GW1NR-UV4QN88C6/I5
Device GW1NR-4B
Created Time Mon Oct 03 18:03:37 2022
Legal Announcement Copyright (C)2014-2022 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module stellar_board
Synthesis Process Running parser:
    CPU time = 0h 0m 1s, Elapsed time = 0h 0m 2s, Peak memory usage = 49.422MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.296s, Elapsed time = 0h 0m 0.297s, Peak memory usage = 49.422MB
    Optimizing Phase 1: CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.135s, Peak memory usage = 49.422MB
    Optimizing Phase 2: CPU time = 0h 0m 0.328s, Elapsed time = 0h 0m 0.341s, Peak memory usage = 49.422MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.121s, Peak memory usage = 49.422MB
    Inferring Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.016s, Peak memory usage = 49.422MB
    Inferring Phase 2: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.041s, Peak memory usage = 49.422MB
    Inferring Phase 3: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.021s, Peak memory usage = 49.422MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.39s, Elapsed time = 0h 0m 0.397s, Peak memory usage = 49.422MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.142s, Peak memory usage = 49.422MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.083s, Peak memory usage = 49.422MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 8s, Elapsed time = 0h 0m 8s, Peak memory usage = 63.113MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.484s, Elapsed time = 0h 0m 0.526s, Peak memory usage = 63.113MB
Generate output files:
    CPU time = 0h 0m 0.281s, Elapsed time = 0h 0m 0.36s, Peak memory usage = 63.113MB
Total Time and Memory Usage CPU time = 0h 0m 11s, Elapsed time = 0h 0m 12s, Peak memory usage = 63.113MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 10
Embedded Port 38
I/O Buf 48
    IBUF 3
    OBUF 29
    IOBUF 16
Register 1631
    DFF 84
    DFFE 816
    DFFS 9
    DFFSE 31
    DFFR 257
    DFFRE 432
    DFFP 2
LUT 1733
    LUT2 162
    LUT3 787
    LUT4 784
ALU 145
    ALU 145
INV 13
    INV 13
IOLOGIC 1
    ODDR 1
BSRAM 5
    SPX9 4
    pROM 1
CLOCK 1
    PLL 1

Resource Utilization Summary

Resource Usage Utilization
Logic 1891(1746 LUTs, 145 ALUs) / 4608 41%
Register 1631 / 3738 44%
  --Register as Latch 0 / 3738 0%
  --Register as FF 1631 / 3738 44%
BSRAM 5 / 10 50%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
clk27 Base 37.037 27.0 0.000 18.519 clk27_ibuf/I
PLL/CLKOUT.default_gen_clk Generated 37.037 27.0 0.000 18.519 clk27_ibuf/I clk27 PLL/CLKOUT
PLL/CLKOUTP.default_gen_clk Generated 37.037 27.0 0.000 18.519 clk27_ibuf/I clk27 PLL/CLKOUTP
PLL/CLKOUTD.default_gen_clk Generated 74.074 13.5 0.000 37.037 clk27_ibuf/I clk27 PLL/CLKOUTD
PLL/CLKOUTD3.default_gen_clk Generated 111.111 9.0 0.000 55.556 clk27_ibuf/I clk27 PLL/CLKOUTD3

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 PLL/CLKOUT.default_gen_clk 27.0(MHz) 80.0(MHz) 9 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 24.534
Data Arrival Time 14.224
Data Required Time 38.758
From storage_1_storage_1_RAMREG_4_G[9]_s0
To main_sdram_dfi_p0_address_10_s0
Launch Clk PLL/CLKOUT.default_gen_clk[R]
Latch Clk PLL/CLKOUT.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 PLL/CLKOUT.default_gen_clk
1.758 1.758 tCL RR 1637 PLL/CLKOUT
2.121 0.363 tNET RR 1 storage_1_storage_1_RAMREG_4_G[9]_s0/CLK
2.579 0.458 tC2Q RF 1 storage_1_storage_1_RAMREG_4_G[9]_s0/Q
3.059 0.480 tNET FF 1 storage_1_RAMOUT_63_G[0]_s3/I1
4.158 1.099 tINS FF 1 storage_1_RAMOUT_63_G[0]_s3/F
4.638 0.480 tNET FF 1 storage_1_RAMOUT_63_G[0]_s1/I0
4.787 0.149 tINS FF 1 storage_1_RAMOUT_63_G[0]_s1/O
5.267 0.480 tNET FF 1 storage_1_RAMOUT_63_G[0]_s0/I0
5.430 0.163 tINS FF 2 storage_1_RAMOUT_63_G[0]_s0/O
5.910 0.480 tNET FF 2 n1922_s0/I0
6.868 0.958 tINS FF 1 n1922_s0/COUT
6.868 0.000 tNET FF 2 n1923_s0/CIN
6.925 0.057 tINS FF 1 n1923_s0/COUT
6.925 0.000 tNET FF 2 n1924_s0/CIN
6.982 0.057 tINS FF 1 n1924_s0/COUT
6.982 0.000 tNET FF 2 n1925_s0/CIN
7.039 0.057 tINS FF 1 n1925_s0/COUT
7.039 0.000 tNET FF 2 n1926_s0/CIN
7.096 0.057 tINS FF 1 n1926_s0/COUT
7.096 0.000 tNET FF 2 n1927_s0/CIN
7.153 0.057 tINS FF 1 n1927_s0/COUT
7.153 0.000 tNET FF 2 n1928_s0/CIN
7.210 0.057 tINS FF 1 n1928_s0/COUT
7.210 0.000 tNET FF 2 n1929_s0/CIN
7.267 0.057 tINS FF 1 n1929_s0/COUT
7.267 0.000 tNET FF 2 n1930_s0/CIN
7.324 0.057 tINS FF 1 n1930_s0/COUT
7.324 0.000 tNET FF 2 n1931_s0/CIN
7.381 0.057 tINS FF 1 n1931_s0/COUT
7.381 0.000 tNET FF 2 n1932_s0/CIN
7.438 0.057 tINS FF 1 n1932_s0/COUT
7.438 0.000 tNET FF 2 n1933_s0/CIN
7.495 0.057 tINS FF 1 n1933_s0/COUT
7.975 0.480 tNET FF 1 builder_array_muxed1_10_s13/I1
9.074 1.099 tINS FF 2 builder_array_muxed1_10_s13/F
9.554 0.480 tNET FF 1 builder_array_muxed1_10_s12/I0
10.586 1.032 tINS FF 1 builder_array_muxed1_10_s12/F
11.066 0.480 tNET FF 1 builder_array_muxed1_10_s6/I1
12.165 1.099 tINS FF 1 builder_array_muxed1_10_s6/F
12.645 0.480 tNET FF 1 builder_array_muxed1_10_s4/I1
13.744 1.099 tINS FF 1 builder_array_muxed1_10_s4/F
14.224 0.480 tNET FF 1 main_sdram_dfi_p0_address_10_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
37.037 0.000 PLL/CLKOUT.default_gen_clk
38.795 1.758 tCL RR 1637 PLL/CLKOUT
39.158 0.363 tNET RR 1 main_sdram_dfi_p0_address_10_s0/CLK
38.758 -0.400 tSu 1 main_sdram_dfi_p0_address_10_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 37.037
Logic Level: 9
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.363, 100.000%
Arrival Data Path Delay: cell: 7.325, 60.520%; route: 4.320, 35.693%; tC2Q: 0.458, 3.787%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.363, 100.000%

Path 2

Path Summary:
Slack 24.551
Data Arrival Time 14.207
Data Required Time 38.758
From main_sdram_bankmachine3_pipe_valid_source_payload_addr_8_s0
To main_sdram_bankmachine3_level_3_s4
Launch Clk PLL/CLKOUT.default_gen_clk[R]
Latch Clk PLL/CLKOUT.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 PLL/CLKOUT.default_gen_clk
1.758 1.758 tCL RR 1637 PLL/CLKOUT
2.121 0.363 tNET RR 1 main_sdram_bankmachine3_pipe_valid_source_payload_addr_8_s0/CLK
2.579 0.458 tC2Q RF 4 main_sdram_bankmachine3_pipe_valid_source_payload_addr_8_s0/Q
3.059 0.480 tNET FF 2 n2702_s0/I1
4.104 1.045 tINS FF 1 n2702_s0/COUT
4.104 0.000 tNET FF 2 n2703_s0/CIN
4.161 0.057 tINS FF 1 n2703_s0/COUT
4.161 0.000 tNET FF 2 n2704_s0/CIN
4.218 0.057 tINS FF 1 n2704_s0/COUT
4.218 0.000 tNET FF 2 n2705_s0/CIN
4.275 0.057 tINS FF 1 n2705_s0/COUT
4.275 0.000 tNET FF 2 n2706_s0/CIN
4.332 0.057 tINS FF 1 n2706_s0/COUT
4.332 0.000 tNET FF 2 n2707_s0/CIN
4.389 0.057 tINS FF 1 n2707_s0/COUT
4.389 0.000 tNET FF 2 n2708_s0/CIN
4.446 0.057 tINS FF 1 n2708_s0/COUT
4.446 0.000 tNET FF 2 n2709_s0/CIN
4.503 0.057 tINS FF 1 n2709_s0/COUT
4.503 0.000 tNET FF 2 n2710_s0/CIN
4.560 0.057 tINS FF 1 n2710_s0/COUT
4.560 0.000 tNET FF 2 n2711_s0/CIN
4.617 0.057 tINS FF 1 n2711_s0/COUT
4.617 0.000 tNET FF 2 n2712_s0/CIN
4.674 0.057 tINS FF 1 n2712_s0/COUT
4.674 0.000 tNET FF 2 n2713_s0/CIN
4.731 0.057 tINS FF 2 n2713_s0/COUT
5.211 0.480 tNET FF 1 builder_basesoc_bankmachine3_next_state_0_s22/I0
6.243 1.032 tINS FF 4 builder_basesoc_bankmachine3_next_state_0_s22/F
6.723 0.480 tNET FF 1 main_sdram_bankmachine3_do_read_s3/I2
7.545 0.822 tINS FF 11 main_sdram_bankmachine3_do_read_s3/F
8.025 0.480 tNET FF 1 main_sdram_bankmachine3_do_read_s2/I0
9.057 1.032 tINS FF 6 main_sdram_bankmachine3_do_read_s2/F
9.537 0.480 tNET FF 1 main_sdram_bankmachine3_do_read_s0/I1
10.636 1.099 tINS FF 6 main_sdram_bankmachine3_do_read_s0/F
11.116 0.480 tNET FF 1 main_sdram_bankmachine3_level_3_s5/I1
12.215 1.099 tINS FF 2 main_sdram_bankmachine3_level_3_s5/F
12.695 0.480 tNET FF 1 n7309_s5/I0
13.727 1.032 tINS FF 1 n7309_s5/F
14.207 0.480 tNET FF 1 main_sdram_bankmachine3_level_3_s4/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
37.037 0.000 PLL/CLKOUT.default_gen_clk
38.795 1.758 tCL RR 1637 PLL/CLKOUT
39.158 0.363 tNET RR 1 main_sdram_bankmachine3_level_3_s4/CLK
38.758 -0.400 tSu 1 main_sdram_bankmachine3_level_3_s4
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 37.037
Logic Level: 10
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.363, 100.000%
Arrival Data Path Delay: cell: 7.788, 64.437%; route: 3.840, 31.771%; tC2Q: 0.458, 3.792%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.363, 100.000%

Path 3

Path Summary:
Slack 24.747
Data Arrival Time 14.011
Data Required Time 38.758
From main_sdram_bankmachine2_pipe_valid_source_payload_addr_8_s0
To main_sdram_bankmachine2_level_3_s4
Launch Clk PLL/CLKOUT.default_gen_clk[R]
Latch Clk PLL/CLKOUT.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 PLL/CLKOUT.default_gen_clk
1.758 1.758 tCL RR 1637 PLL/CLKOUT
2.121 0.363 tNET RR 1 main_sdram_bankmachine2_pipe_valid_source_payload_addr_8_s0/CLK
2.579 0.458 tC2Q RF 4 main_sdram_bankmachine2_pipe_valid_source_payload_addr_8_s0/Q
3.059 0.480 tNET FF 2 n2295_s0/I1
4.104 1.045 tINS FF 1 n2295_s0/COUT
4.104 0.000 tNET FF 2 n2296_s0/CIN
4.161 0.057 tINS FF 1 n2296_s0/COUT
4.161 0.000 tNET FF 2 n2297_s0/CIN
4.218 0.057 tINS FF 1 n2297_s0/COUT
4.218 0.000 tNET FF 2 n2298_s0/CIN
4.275 0.057 tINS FF 1 n2298_s0/COUT
4.275 0.000 tNET FF 2 n2299_s0/CIN
4.332 0.057 tINS FF 1 n2299_s0/COUT
4.332 0.000 tNET FF 2 n2300_s0/CIN
4.389 0.057 tINS FF 1 n2300_s0/COUT
4.389 0.000 tNET FF 2 n2301_s0/CIN
4.446 0.057 tINS FF 1 n2301_s0/COUT
4.446 0.000 tNET FF 2 n2302_s0/CIN
4.503 0.057 tINS FF 1 n2302_s0/COUT
4.503 0.000 tNET FF 2 n2303_s0/CIN
4.560 0.057 tINS FF 1 n2303_s0/COUT
4.560 0.000 tNET FF 2 n2304_s0/CIN
4.617 0.057 tINS FF 1 n2304_s0/COUT
4.617 0.000 tNET FF 2 n2305_s0/CIN
4.674 0.057 tINS FF 1 n2305_s0/COUT
4.674 0.000 tNET FF 2 n2306_s0/CIN
4.731 0.057 tINS FF 3 n2306_s0/COUT
5.211 0.480 tNET FF 1 main_sdram_bankmachine2_do_read_s7/I0
6.243 1.032 tINS FF 3 main_sdram_bankmachine2_do_read_s7/F
6.723 0.480 tNET FF 1 main_sdram_bankmachine2_do_read_s3/I3
7.349 0.626 tINS FF 11 main_sdram_bankmachine2_do_read_s3/F
7.829 0.480 tNET FF 1 main_sdram_bankmachine2_do_read_s2/I0
8.861 1.032 tINS FF 6 main_sdram_bankmachine2_do_read_s2/F
9.341 0.480 tNET FF 1 main_sdram_bankmachine2_do_read_s0/I1
10.440 1.099 tINS FF 6 main_sdram_bankmachine2_do_read_s0/F
10.920 0.480 tNET FF 1 main_sdram_bankmachine2_level_3_s5/I1
12.019 1.099 tINS FF 2 main_sdram_bankmachine2_level_3_s5/F
12.499 0.480 tNET FF 1 n7205_s5/I0
13.531 1.032 tINS FF 1 n7205_s5/F
14.011 0.480 tNET FF 1 main_sdram_bankmachine2_level_3_s4/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
37.037 0.000 PLL/CLKOUT.default_gen_clk
38.795 1.758 tCL RR 1637 PLL/CLKOUT
39.158 0.363 tNET RR 1 main_sdram_bankmachine2_level_3_s4/CLK
38.758 -0.400 tSu 1 main_sdram_bankmachine2_level_3_s4
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 37.037
Logic Level: 10
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.363, 100.000%
Arrival Data Path Delay: cell: 7.592, 63.850%; route: 3.840, 32.295%; tC2Q: 0.458, 3.855%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.363, 100.000%

Path 4

Path Summary:
Slack 25.074
Data Arrival Time 13.684
Data Required Time 38.758
From storage_1_storage_1_RAMREG_4_G[9]_s0
To builder_basesoc_bankmachine1_state_1_s1
Launch Clk PLL/CLKOUT.default_gen_clk[R]
Latch Clk PLL/CLKOUT.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 PLL/CLKOUT.default_gen_clk
1.758 1.758 tCL RR 1637 PLL/CLKOUT
2.121 0.363 tNET RR 1 storage_1_storage_1_RAMREG_4_G[9]_s0/CLK
2.579 0.458 tC2Q RF 1 storage_1_storage_1_RAMREG_4_G[9]_s0/Q
3.059 0.480 tNET FF 1 storage_1_RAMOUT_63_G[0]_s3/I1
4.158 1.099 tINS FF 1 storage_1_RAMOUT_63_G[0]_s3/F
4.638 0.480 tNET FF 1 storage_1_RAMOUT_63_G[0]_s1/I0
4.787 0.149 tINS FF 1 storage_1_RAMOUT_63_G[0]_s1/O
5.267 0.480 tNET FF 1 storage_1_RAMOUT_63_G[0]_s0/I0
5.430 0.163 tINS FF 2 storage_1_RAMOUT_63_G[0]_s0/O
5.910 0.480 tNET FF 2 n1922_s0/I0
6.868 0.958 tINS FF 1 n1922_s0/COUT
6.868 0.000 tNET FF 2 n1923_s0/CIN
6.925 0.057 tINS FF 1 n1923_s0/COUT
6.925 0.000 tNET FF 2 n1924_s0/CIN
6.982 0.057 tINS FF 1 n1924_s0/COUT
6.982 0.000 tNET FF 2 n1925_s0/CIN
7.039 0.057 tINS FF 1 n1925_s0/COUT
7.039 0.000 tNET FF 2 n1926_s0/CIN
7.096 0.057 tINS FF 1 n1926_s0/COUT
7.096 0.000 tNET FF 2 n1927_s0/CIN
7.153 0.057 tINS FF 1 n1927_s0/COUT
7.153 0.000 tNET FF 2 n1928_s0/CIN
7.210 0.057 tINS FF 1 n1928_s0/COUT
7.210 0.000 tNET FF 2 n1929_s0/CIN
7.267 0.057 tINS FF 1 n1929_s0/COUT
7.267 0.000 tNET FF 2 n1930_s0/CIN
7.324 0.057 tINS FF 1 n1930_s0/COUT
7.324 0.000 tNET FF 2 n1931_s0/CIN
7.381 0.057 tINS FF 1 n1931_s0/COUT
7.381 0.000 tNET FF 2 n1932_s0/CIN
7.438 0.057 tINS FF 1 n1932_s0/COUT
7.438 0.000 tNET FF 2 n1933_s0/CIN
7.495 0.057 tINS FF 1 n1933_s0/COUT
7.975 0.480 tNET FF 1 builder_array_muxed1_10_s13/I1
9.074 1.099 tINS FF 2 builder_array_muxed1_10_s13/F
9.554 0.480 tNET FF 1 builder_basesoc_bankmachine1_state_2_s6/I3
10.180 0.626 tINS FF 2 builder_basesoc_bankmachine1_state_2_s6/F
10.660 0.480 tNET FF 1 builder_basesoc_bankmachine1_next_state_1_s23/I0
11.692 1.032 tINS FF 1 builder_basesoc_bankmachine1_next_state_1_s23/F
12.172 0.480 tNET FF 1 builder_basesoc_bankmachine1_next_state_1_s22/I0
13.204 1.032 tINS FF 1 builder_basesoc_bankmachine1_next_state_1_s22/F
13.684 0.480 tNET FF 1 builder_basesoc_bankmachine1_state_1_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
37.037 0.000 PLL/CLKOUT.default_gen_clk
38.795 1.758 tCL RR 1637 PLL/CLKOUT
39.158 0.363 tNET RR 1 builder_basesoc_bankmachine1_state_1_s1/CLK
38.758 -0.400 tSu 1 builder_basesoc_bankmachine1_state_1_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 37.037
Logic Level: 9
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.363, 100.000%
Arrival Data Path Delay: cell: 6.785, 58.677%; route: 4.320, 37.359%; tC2Q: 0.458, 3.964%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.363, 100.000%

Path 5

Path Summary:
Slack 25.357
Data Arrival Time 13.757
Data Required Time 39.114
From storage_storage_RAMREG_4_G[9]_s0
To builder_basesoc_bankmachine0_state_0_s1
Launch Clk PLL/CLKOUT.default_gen_clk[R]
Latch Clk PLL/CLKOUT.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 PLL/CLKOUT.default_gen_clk
1.758 1.758 tCL RR 1637 PLL/CLKOUT
2.121 0.363 tNET RR 1 storage_storage_RAMREG_4_G[9]_s0/CLK
2.579 0.458 tC2Q RF 1 storage_storage_RAMREG_4_G[9]_s0/Q
3.059 0.480 tNET FF 1 storage_RAMOUT_63_G[0]_s3/I1
4.158 1.099 tINS FF 1 storage_RAMOUT_63_G[0]_s3/F
4.638 0.480 tNET FF 1 storage_RAMOUT_63_G[0]_s1/I0
4.787 0.149 tINS FF 1 storage_RAMOUT_63_G[0]_s1/O
5.267 0.480 tNET FF 1 storage_RAMOUT_63_G[0]_s0/I0
5.430 0.163 tINS FF 2 storage_RAMOUT_63_G[0]_s0/O
5.910 0.480 tNET FF 2 n1515_s0/I0
6.868 0.958 tINS FF 1 n1515_s0/COUT
6.868 0.000 tNET FF 2 n1516_s0/CIN
6.925 0.057 tINS FF 1 n1516_s0/COUT
6.925 0.000 tNET FF 2 n1517_s0/CIN
6.982 0.057 tINS FF 1 n1517_s0/COUT
6.982 0.000 tNET FF 2 n1518_s0/CIN
7.039 0.057 tINS FF 1 n1518_s0/COUT
7.039 0.000 tNET FF 2 n1519_s0/CIN
7.096 0.057 tINS FF 1 n1519_s0/COUT
7.096 0.000 tNET FF 2 n1520_s0/CIN
7.153 0.057 tINS FF 1 n1520_s0/COUT
7.153 0.000 tNET FF 2 n1521_s0/CIN
7.210 0.057 tINS FF 1 n1521_s0/COUT
7.210 0.000 tNET FF 2 n1522_s0/CIN
7.267 0.057 tINS FF 1 n1522_s0/COUT
7.267 0.000 tNET FF 2 n1523_s0/CIN
7.324 0.057 tINS FF 1 n1523_s0/COUT
7.324 0.000 tNET FF 2 n1524_s0/CIN
7.381 0.057 tINS FF 1 n1524_s0/COUT
7.381 0.000 tNET FF 2 n1525_s0/CIN
7.438 0.057 tINS FF 1 n1525_s0/COUT
7.438 0.000 tNET FF 2 n1526_s0/CIN
7.495 0.057 tINS FF 1 n1526_s0/COUT
7.975 0.480 tNET FF 1 builder_basesoc_bankmachine0_next_state_1_s26/I1
9.074 1.099 tINS FF 2 builder_basesoc_bankmachine0_next_state_1_s26/F
9.554 0.480 tNET FF 1 builder_basesoc_bankmachine0_next_state_1_s23/I2
10.376 0.822 tINS FF 2 builder_basesoc_bankmachine0_next_state_1_s23/F
10.856 0.480 tNET FF 1 builder_basesoc_bankmachine0_state_2_s8/I0
11.888 1.032 tINS FF 1 builder_basesoc_bankmachine0_state_2_s8/F
12.368 0.480 tNET FF 1 builder_basesoc_bankmachine0_state_2_s3/I0
13.394 1.026 tINS FR 3 builder_basesoc_bankmachine0_state_2_s3/F
13.757 0.363 tNET RR 1 builder_basesoc_bankmachine0_state_0_s1/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
37.037 0.000 PLL/CLKOUT.default_gen_clk
38.795 1.758 tCL RR 1637 PLL/CLKOUT
39.158 0.363 tNET RR 1 builder_basesoc_bankmachine0_state_0_s1/CLK
39.114 -0.043 tSu 1 builder_basesoc_bankmachine0_state_0_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 37.037
Logic Level: 9
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.363, 100.000%
Arrival Data Path Delay: cell: 6.975, 59.941%; route: 4.203, 36.120%; tC2Q: 0.458, 3.939%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.363, 100.000%