//-------------------------------------------------------------------------------- // Auto-generated by Migen (7507a2b) & LiteX (57002cf3) on 2021-10-20 06:56:16 //-------------------------------------------------------------------------------- module _1bitsquared_icebreaker( input wire serial_rx, output reg serial_tx, (* keep = "true" *) input wire clk12, input wire user_btn_n, output wire spiflash_cs_n, inout wire spiflash_clk, inout wire spiflash_miso, inout wire spiflash_mosi, input wire spiflash_wp, input wire spiflash_hold, output reg user_led0, output reg user_led1, output reg user_led2, output reg user_led3, output reg user_led4 ); reg main_soc_rst = 1'd0; wire main_cpu_rst; reg [1:0] main_reset_storage = 2'd0; reg main_reset_re = 1'd0; reg [31:0] main_scratch_storage = 32'd305419896; reg main_scratch_re = 1'd0; wire [31:0] main_bus_errors_status; wire main_bus_errors_we; reg main_bus_errors_re = 1'd0; wire main_bus_error; reg [31:0] main_bus_errors = 32'd0; wire main_serv_reset; wire [29:0] main_serv_ibus_adr; reg [31:0] main_serv_ibus_dat_w = 32'd0; wire [31:0] main_serv_ibus_dat_r; wire [3:0] main_serv_ibus_sel; wire main_serv_ibus_cyc; wire main_serv_ibus_stb; wire main_serv_ibus_ack; reg main_serv_ibus_we = 1'd0; reg [2:0] main_serv_ibus_cti = 3'd0; reg [1:0] main_serv_ibus_bte = 2'd0; wire main_serv_ibus_err; wire [29:0] main_serv_dbus_adr; wire [31:0] main_serv_dbus_dat_w; wire [31:0] main_serv_dbus_dat_r; wire [3:0] main_serv_dbus_sel; wire main_serv_dbus_cyc; wire main_serv_dbus_stb; wire main_serv_dbus_ack; wire main_serv_dbus_we; reg [2:0] main_serv_dbus_cti = 3'd0; reg [1:0] main_serv_dbus_bte = 2'd0; wire main_serv_dbus_err; wire [1:0] main_serv0; wire [1:0] main_serv1; wire main_tx_sink_valid; reg main_tx_sink_ready = 1'd0; wire main_tx_sink_first; wire main_tx_sink_last; wire [7:0] main_tx_sink_payload_data; reg [7:0] main_tx_data = 8'd0; reg [3:0] main_tx_count = 4'd0; reg main_tx_enable = 1'd0; reg main_tx_tick = 1'd0; reg [31:0] main_tx_phase = 32'd0; reg main_rx_source_valid = 1'd0; wire main_rx_source_ready; reg main_rx_source_first = 1'd0; reg main_rx_source_last = 1'd0; reg [7:0] main_rx_source_payload_data = 8'd0; reg [7:0] main_rx_data = 8'd0; reg [3:0] main_rx_count = 4'd0; reg main_rx_enable = 1'd0; reg main_rx_tick = 1'd0; reg [31:0] main_rx_phase = 32'd0; wire main_rx_rx; reg main_rx_rx_d = 1'd0; reg main_uart_rxtx_re = 1'd0; wire [7:0] main_uart_rxtx_r; reg main_uart_rxtx_we = 1'd0; wire [7:0] main_uart_rxtx_w; wire main_uart_txfull_status; wire main_uart_txfull_we; reg main_uart_txfull_re = 1'd0; wire main_uart_rxempty_status; wire main_uart_rxempty_we; reg main_uart_rxempty_re = 1'd0; wire main_uart_irq; wire main_uart_tx_status; reg main_uart_tx_pending = 1'd0; wire main_uart_tx_trigger; reg main_uart_tx_clear = 1'd0; reg main_uart_tx_trigger_d = 1'd0; wire main_uart_rx_status; reg main_uart_rx_pending = 1'd0; wire main_uart_rx_trigger; reg main_uart_rx_clear = 1'd0; reg main_uart_rx_trigger_d = 1'd0; wire main_uart_tx0; wire main_uart_rx0; reg [1:0] main_uart_status_status = 2'd0; wire main_uart_status_we; reg main_uart_status_re = 1'd0; wire main_uart_tx1; wire main_uart_rx1; reg [1:0] main_uart_pending_status = 2'd0; wire main_uart_pending_we; reg main_uart_pending_re = 1'd0; reg [1:0] main_uart_pending_r = 2'd0; wire main_uart_tx2; wire main_uart_rx2; reg [1:0] main_uart_enable_storage = 2'd0; reg main_uart_enable_re = 1'd0; wire main_uart_txempty_status; wire main_uart_txempty_we; reg main_uart_txempty_re = 1'd0; wire main_uart_rxfull_status; wire main_uart_rxfull_we; reg main_uart_rxfull_re = 1'd0; wire main_uart_uart_sink_valid; wire main_uart_uart_sink_ready; wire main_uart_uart_sink_first; wire main_uart_uart_sink_last; wire [7:0] main_uart_uart_sink_payload_data; wire main_uart_uart_source_valid; wire main_uart_uart_source_ready; wire main_uart_uart_source_first; wire main_uart_uart_source_last; wire [7:0] main_uart_uart_source_payload_data; wire main_uart_tx_fifo_sink_valid; wire main_uart_tx_fifo_sink_ready; reg main_uart_tx_fifo_sink_first = 1'd0; reg main_uart_tx_fifo_sink_last = 1'd0; wire [7:0] main_uart_tx_fifo_sink_payload_data; wire main_uart_tx_fifo_source_valid; wire main_uart_tx_fifo_source_ready; wire main_uart_tx_fifo_source_first; wire main_uart_tx_fifo_source_last; wire [7:0] main_uart_tx_fifo_source_payload_data; wire main_uart_tx_fifo_re; reg main_uart_tx_fifo_readable = 1'd0; wire main_uart_tx_fifo_syncfifo_we; wire main_uart_tx_fifo_syncfifo_writable; wire main_uart_tx_fifo_syncfifo_re; wire main_uart_tx_fifo_syncfifo_readable; wire [9:0] main_uart_tx_fifo_syncfifo_din; wire [9:0] main_uart_tx_fifo_syncfifo_dout; reg [4:0] main_uart_tx_fifo_level0 = 5'd0; reg main_uart_tx_fifo_replace = 1'd0; reg [3:0] main_uart_tx_fifo_produce = 4'd0; reg [3:0] main_uart_tx_fifo_consume = 4'd0; reg [3:0] main_uart_tx_fifo_wrport_adr = 4'd0; wire [9:0] main_uart_tx_fifo_wrport_dat_r; wire main_uart_tx_fifo_wrport_we; wire [9:0] main_uart_tx_fifo_wrport_dat_w; wire main_uart_tx_fifo_do_read; wire [3:0] main_uart_tx_fifo_rdport_adr; wire [9:0] main_uart_tx_fifo_rdport_dat_r; wire main_uart_tx_fifo_rdport_re; wire [4:0] main_uart_tx_fifo_level1; wire [7:0] main_uart_tx_fifo_fifo_in_payload_data; wire main_uart_tx_fifo_fifo_in_first; wire main_uart_tx_fifo_fifo_in_last; wire [7:0] main_uart_tx_fifo_fifo_out_payload_data; wire main_uart_tx_fifo_fifo_out_first; wire main_uart_tx_fifo_fifo_out_last; wire main_uart_rx_fifo_sink_valid; wire main_uart_rx_fifo_sink_ready; wire main_uart_rx_fifo_sink_first; wire main_uart_rx_fifo_sink_last; wire [7:0] main_uart_rx_fifo_sink_payload_data; wire main_uart_rx_fifo_source_valid; wire main_uart_rx_fifo_source_ready; wire main_uart_rx_fifo_source_first; wire main_uart_rx_fifo_source_last; wire [7:0] main_uart_rx_fifo_source_payload_data; wire main_uart_rx_fifo_re; reg main_uart_rx_fifo_readable = 1'd0; wire main_uart_rx_fifo_syncfifo_we; wire main_uart_rx_fifo_syncfifo_writable; wire main_uart_rx_fifo_syncfifo_re; wire main_uart_rx_fifo_syncfifo_readable; wire [9:0] main_uart_rx_fifo_syncfifo_din; wire [9:0] main_uart_rx_fifo_syncfifo_dout; reg [4:0] main_uart_rx_fifo_level0 = 5'd0; reg main_uart_rx_fifo_replace = 1'd0; reg [3:0] main_uart_rx_fifo_produce = 4'd0; reg [3:0] main_uart_rx_fifo_consume = 4'd0; reg [3:0] main_uart_rx_fifo_wrport_adr = 4'd0; wire [9:0] main_uart_rx_fifo_wrport_dat_r; wire main_uart_rx_fifo_wrport_we; wire [9:0] main_uart_rx_fifo_wrport_dat_w; wire main_uart_rx_fifo_do_read; wire [3:0] main_uart_rx_fifo_rdport_adr; wire [9:0] main_uart_rx_fifo_rdport_dat_r; wire main_uart_rx_fifo_rdport_re; wire [4:0] main_uart_rx_fifo_level1; wire [7:0] main_uart_rx_fifo_fifo_in_payload_data; wire main_uart_rx_fifo_fifo_in_first; wire main_uart_rx_fifo_fifo_in_last; wire [7:0] main_uart_rx_fifo_fifo_out_payload_data; wire main_uart_rx_fifo_fifo_out_first; wire main_uart_rx_fifo_fifo_out_last; reg [31:0] main_timer_load_storage = 32'd0; reg main_timer_load_re = 1'd0; reg [31:0] main_timer_reload_storage = 32'd0; reg main_timer_reload_re = 1'd0; reg main_timer_en_storage = 1'd0; reg main_timer_en_re = 1'd0; reg main_timer_update_value_storage = 1'd0; reg main_timer_update_value_re = 1'd0; reg [31:0] main_timer_value_status = 32'd0; wire main_timer_value_we; reg main_timer_value_re = 1'd0; wire main_timer_irq; wire main_timer_zero_status; reg main_timer_zero_pending = 1'd0; wire main_timer_zero_trigger; reg main_timer_zero_clear = 1'd0; reg main_timer_zero_trigger_d = 1'd0; wire main_timer_zero0; wire main_timer_status_status; wire main_timer_status_we; reg main_timer_status_re = 1'd0; wire main_timer_zero1; wire main_timer_pending_status; wire main_timer_pending_we; reg main_timer_pending_re = 1'd0; reg main_timer_pending_r = 1'd0; wire main_timer_zero2; reg main_timer_enable_storage = 1'd0; reg main_timer_enable_re = 1'd0; reg [31:0] main_timer_value = 32'd0; wire main_rst; (* keep = "true" *) wire sys_clk; wire sys_rst; wire por_clk; reg [15:0] main_por_count = 16'd65535; wire main_por_done; wire main_reset; wire main_locked; wire main_clkin; wire main_clkout; wire [29:0] main_bus_adr; wire [31:0] main_bus_dat_w; reg [31:0] main_bus_dat_r = 32'd0; wire [3:0] main_bus_sel; wire main_bus_cyc; wire main_bus_stb; reg main_bus_ack = 1'd0; wire main_bus_we; wire [2:0] main_bus_cti; wire [1:0] main_bus_bte; reg main_bus_err = 1'd0; wire [15:0] main_datain0; wire [15:0] main_dataout0; reg [3:0] main_maskwren0 = 4'd0; reg main_wren0 = 1'd0; wire [15:0] main_datain1; wire [15:0] main_dataout1; reg [3:0] main_maskwren1 = 4'd0; reg main_wren1 = 1'd0; wire [15:0] main_datain2; wire [15:0] main_dataout2; reg [3:0] main_maskwren2 = 4'd0; reg main_wren2 = 1'd0; wire [15:0] main_datain3; wire [15:0] main_dataout3; reg [3:0] main_maskwren3 = 4'd0; reg main_wren3 = 1'd0; reg main_litespisdrphycore_source_valid = 1'd0; wire main_litespisdrphycore_source_ready; reg main_litespisdrphycore_source_first = 1'd0; reg main_litespisdrphycore_source_last = 1'd0; wire [31:0] main_litespisdrphycore_source_payload_data; wire main_litespisdrphycore_sink_valid; reg main_litespisdrphycore_sink_ready = 1'd0; wire main_litespisdrphycore_sink_first; wire main_litespisdrphycore_sink_last; wire [31:0] main_litespisdrphycore_sink_payload_data; wire [5:0] main_litespisdrphycore_sink_payload_len; wire [3:0] main_litespisdrphycore_sink_payload_width; wire [7:0] main_litespisdrphycore_sink_payload_mask; wire main_litespisdrphycore_cs; wire [7:0] main_litespisdrphycore_spi_clk_divisor; reg [7:0] main_litespisdrphycore_storage = 8'd1; reg main_litespisdrphycore_re = 1'd0; wire [7:0] main_litespisdrphycore_div; wire [7:0] main_litespisdrphycore_sample_cnt; wire [7:0] main_litespisdrphycore_update_cnt; wire main_litespisdrphycore_posedge; wire main_litespisdrphycore_negedge; wire main_litespisdrphycore_sample; wire main_litespisdrphycore_update; reg main_litespisdrphycore_en = 1'd0; reg [7:0] main_litespisdrphycore_cnt = 8'd0; reg main_litespisdrphycore_en_int = 1'd0; reg main_litespisdrphycore_clk = 1'd0; reg main_litespisdrphycore_posedge_reg = 1'd0; reg main_litespisdrphycore_posedge_reg2 = 1'd0; wire main_litespisdrphycore_wait; wire main_litespisdrphycore_done; reg [3:0] main_litespisdrphycore_count = 4'd11; wire main_litespisdrphycore_cs_enable; reg main_litespisdrphycore_dq_o = 1'd0; wire main_litespisdrphycore_dq_i; wire main_litespisdrphycore_dq_oe; reg [7:0] main_litespisdrphycore_sr_cnt = 8'd0; reg main_litespisdrphycore_sr_out_load = 1'd0; reg main_litespisdrphycore_sr_out_shift = 1'd0; reg [31:0] main_litespisdrphycore_sr_out = 32'd0; reg main_litespisdrphycore_sr_in_shift = 1'd0; reg [31:0] main_litespisdrphycore_sr_in = 32'd0; reg main_litespisdrphycore0 = 1'd0; reg [1:0] main_litespisdrphycore1 = 2'd0; reg [3:0] main_litespisdrphycore2 = 4'd0; reg [7:0] main_litespisdrphycore3 = 8'd0; wire main_source_valid; wire main_source_ready; wire main_source_first; wire main_source_last; wire [31:0] main_source_payload_data; wire [5:0] main_source_payload_len; wire [3:0] main_source_payload_width; wire [7:0] main_source_payload_mask; wire main_sink_valid; wire main_sink_ready; wire main_sink_first; wire main_sink_last; wire [31:0] main_sink_payload_data; reg main_cs = 1'd0; reg main_litespimmap_source_valid = 1'd0; wire main_litespimmap_source_ready; reg main_litespimmap_source_first = 1'd0; reg main_litespimmap_source_last = 1'd0; reg [31:0] main_litespimmap_source_payload_data = 32'd0; reg [5:0] main_litespimmap_source_payload_len = 6'd0; reg [3:0] main_litespimmap_source_payload_width = 4'd0; reg [7:0] main_litespimmap_source_payload_mask = 8'd0; wire main_litespimmap_sink_valid; reg main_litespimmap_sink_ready = 1'd0; wire main_litespimmap_sink_first; wire main_litespimmap_sink_last; wire [31:0] main_litespimmap_sink_payload_data; wire [29:0] main_litespimmap_bus_adr; wire [31:0] main_litespimmap_bus_dat_w; reg [31:0] main_litespimmap_bus_dat_r = 32'd0; wire [3:0] main_litespimmap_bus_sel; wire main_litespimmap_bus_cyc; wire main_litespimmap_bus_stb; reg main_litespimmap_bus_ack = 1'd0; wire main_litespimmap_bus_we; wire [2:0] main_litespimmap_bus_cti; wire [1:0] main_litespimmap_bus_bte; reg main_litespimmap_bus_err = 1'd0; reg main_litespimmap_cs = 1'd0; reg main_litespimmap_burst_cs = 1'd0; reg [29:0] main_litespimmap_burst_adr = 30'd0; reg main_litespimmap_wait = 1'd0; wire main_litespimmap_done; reg [8:0] main_litespimmap_count = 9'd256; reg [7:0] main_litespimmap_storage = 8'd0; reg main_litespimmap_re = 1'd0; wire [7:0] main_litespimmap_spi_dummy_bits; reg [31:0] main_litespimmap_dummy = 32'd57005; reg [1:0] main_litespimmap = 2'd0; wire main_user_port_source_valid; wire main_user_port_source_ready; wire main_user_port_source_first; wire main_user_port_source_last; wire [31:0] main_user_port_source_payload_data; wire main_user_port_sink_valid; wire main_user_port_sink_ready; wire main_user_port_sink_first; wire main_user_port_sink_last; wire [31:0] main_user_port_sink_payload_data; wire [5:0] main_user_port_sink_payload_len; wire [3:0] main_user_port_sink_payload_width; wire [7:0] main_user_port_sink_payload_mask; wire main_internal_port_source_valid; wire main_internal_port_source_ready; wire main_internal_port_source_first; wire main_internal_port_source_last; wire [31:0] main_internal_port_source_payload_data; wire main_internal_port_sink_valid; wire main_internal_port_sink_ready; wire main_internal_port_sink_first; wire main_internal_port_sink_last; wire [31:0] main_internal_port_sink_payload_data; wire [5:0] main_internal_port_sink_payload_len; wire [3:0] main_internal_port_sink_payload_width; wire [7:0] main_internal_port_sink_payload_mask; wire main_request; reg [4:0] main_storage = 5'd0; reg main_re = 1'd0; reg [4:0] main_chaser = 5'd0; reg main_mode = 1'd0; wire main_wait; wire main_done; reg [21:0] main_count = 22'd2400000; reg builder_rs232phytx_state = 1'd0; reg builder_rs232phytx_next_state = 1'd0; reg [3:0] main_tx_count_rs232phytx_next_value0 = 4'd0; reg main_tx_count_rs232phytx_next_value_ce0 = 1'd0; reg main_serial_tx_rs232phytx_next_value1 = 1'd0; reg main_serial_tx_rs232phytx_next_value_ce1 = 1'd0; reg [7:0] main_tx_data_rs232phytx_next_value2 = 8'd0; reg main_tx_data_rs232phytx_next_value_ce2 = 1'd0; reg builder_rs232phyrx_state = 1'd0; reg builder_rs232phyrx_next_state = 1'd0; reg [3:0] main_rx_count_rs232phyrx_next_value0 = 4'd0; reg main_rx_count_rs232phyrx_next_value_ce0 = 1'd0; reg [7:0] main_rx_data_rs232phyrx_next_value1 = 8'd0; reg main_rx_data_rs232phyrx_next_value_ce1 = 1'd0; reg [1:0] builder_litespiphy_state = 2'd0; reg [1:0] builder_litespiphy_next_state = 2'd0; reg [7:0] main_litespisdrphycore_sr_cnt_litespiphy_next_value = 8'd0; reg main_litespisdrphycore_sr_cnt_litespiphy_next_value_ce = 1'd0; wire builder_litespi_request; wire builder_litespi_grant; reg builder_litespi_tx_mux_source_valid = 1'd0; wire builder_litespi_tx_mux_source_ready; reg builder_litespi_tx_mux_source_first = 1'd0; reg builder_litespi_tx_mux_source_last = 1'd0; reg [31:0] builder_litespi_tx_mux_source_payload_data = 32'd0; reg [5:0] builder_litespi_tx_mux_source_payload_len = 6'd0; reg [3:0] builder_litespi_tx_mux_source_payload_width = 4'd0; reg [7:0] builder_litespi_tx_mux_source_payload_mask = 8'd0; wire builder_litespi_tx_mux_sink_valid; reg builder_litespi_tx_mux_sink_ready = 1'd0; wire builder_litespi_tx_mux_sink_first; wire builder_litespi_tx_mux_sink_last; wire [31:0] builder_litespi_tx_mux_sink_payload_data; wire [5:0] builder_litespi_tx_mux_sink_payload_len; wire [3:0] builder_litespi_tx_mux_sink_payload_width; wire [7:0] builder_litespi_tx_mux_sink_payload_mask; wire builder_litespi_tx_mux_sel; wire builder_litespi_rx_demux_sink_valid; reg builder_litespi_rx_demux_sink_ready = 1'd0; wire builder_litespi_rx_demux_sink_first; wire builder_litespi_rx_demux_sink_last; wire [31:0] builder_litespi_rx_demux_sink_payload_data; reg builder_litespi_rx_demux_source_valid = 1'd0; wire builder_litespi_rx_demux_source_ready; reg builder_litespi_rx_demux_source_first = 1'd0; reg builder_litespi_rx_demux_source_last = 1'd0; reg [31:0] builder_litespi_rx_demux_source_payload_data = 32'd0; wire builder_litespi_rx_demux_sel; reg [3:0] builder_litespi_state = 4'd0; reg [3:0] builder_litespi_next_state = 4'd0; reg main_litespimmap_burst_cs_litespi_next_value0 = 1'd0; reg main_litespimmap_burst_cs_litespi_next_value_ce0 = 1'd0; reg [29:0] main_litespimmap_burst_adr_litespi_next_value1 = 30'd0; reg main_litespimmap_burst_adr_litespi_next_value_ce1 = 1'd0; reg [13:0] builder_basesoc_adr = 14'd0; reg builder_basesoc_we = 1'd0; reg [31:0] builder_basesoc_dat_w = 32'd0; wire [31:0] builder_basesoc_dat_r; wire [29:0] builder_basesoc_wishbone_adr; wire [31:0] builder_basesoc_wishbone_dat_w; reg [31:0] builder_basesoc_wishbone_dat_r = 32'd0; wire [3:0] builder_basesoc_wishbone_sel; wire builder_basesoc_wishbone_cyc; wire builder_basesoc_wishbone_stb; reg builder_basesoc_wishbone_ack = 1'd0; wire builder_basesoc_wishbone_we; wire [2:0] builder_basesoc_wishbone_cti; wire [1:0] builder_basesoc_wishbone_bte; reg builder_basesoc_wishbone_err = 1'd0; wire [29:0] builder_shared_adr; wire [31:0] builder_shared_dat_w; reg [31:0] builder_shared_dat_r = 32'd0; wire [3:0] builder_shared_sel; wire builder_shared_cyc; wire builder_shared_stb; reg builder_shared_ack = 1'd0; wire builder_shared_we; wire [2:0] builder_shared_cti; wire [1:0] builder_shared_bte; wire builder_shared_err; wire [1:0] builder_request; reg builder_grant = 1'd0; reg [2:0] builder_slave_sel = 3'd0; reg [2:0] builder_slave_sel_r = 3'd0; reg builder_error = 1'd0; wire builder_wait; wire builder_done; reg [19:0] builder_count = 20'd1000000; wire [13:0] builder_csr_bankarray_interface0_bank_bus_adr; wire builder_csr_bankarray_interface0_bank_bus_we; wire [31:0] builder_csr_bankarray_interface0_bank_bus_dat_w; reg [31:0] builder_csr_bankarray_interface0_bank_bus_dat_r = 32'd0; reg builder_csr_bankarray_csrbank0_reset0_re = 1'd0; wire [1:0] builder_csr_bankarray_csrbank0_reset0_r; reg builder_csr_bankarray_csrbank0_reset0_we = 1'd0; wire [1:0] builder_csr_bankarray_csrbank0_reset0_w; reg builder_csr_bankarray_csrbank0_scratch0_re = 1'd0; wire [31:0] builder_csr_bankarray_csrbank0_scratch0_r; reg builder_csr_bankarray_csrbank0_scratch0_we = 1'd0; wire [31:0] builder_csr_bankarray_csrbank0_scratch0_w; reg builder_csr_bankarray_csrbank0_bus_errors_re = 1'd0; wire [31:0] builder_csr_bankarray_csrbank0_bus_errors_r; reg builder_csr_bankarray_csrbank0_bus_errors_we = 1'd0; wire [31:0] builder_csr_bankarray_csrbank0_bus_errors_w; wire builder_csr_bankarray_csrbank0_sel; wire [13:0] builder_csr_bankarray_sram_bus_adr; wire builder_csr_bankarray_sram_bus_we; wire [31:0] builder_csr_bankarray_sram_bus_dat_w; reg [31:0] builder_csr_bankarray_sram_bus_dat_r = 32'd0; wire [5:0] builder_csr_bankarray_adr; wire [7:0] builder_csr_bankarray_dat_r; wire builder_csr_bankarray_sel; reg builder_csr_bankarray_sel_r = 1'd0; wire [13:0] builder_csr_bankarray_interface1_bank_bus_adr; wire builder_csr_bankarray_interface1_bank_bus_we; wire [31:0] builder_csr_bankarray_interface1_bank_bus_dat_w; reg [31:0] builder_csr_bankarray_interface1_bank_bus_dat_r = 32'd0; reg builder_csr_bankarray_csrbank1_out0_re = 1'd0; wire [4:0] builder_csr_bankarray_csrbank1_out0_r; reg builder_csr_bankarray_csrbank1_out0_we = 1'd0; wire [4:0] builder_csr_bankarray_csrbank1_out0_w; wire builder_csr_bankarray_csrbank1_sel; wire [13:0] builder_csr_bankarray_interface2_bank_bus_adr; wire builder_csr_bankarray_interface2_bank_bus_we; wire [31:0] builder_csr_bankarray_interface2_bank_bus_dat_w; reg [31:0] builder_csr_bankarray_interface2_bank_bus_dat_r = 32'd0; reg builder_csr_bankarray_csrbank2_mmap_dummy_bits0_re = 1'd0; wire [7:0] builder_csr_bankarray_csrbank2_mmap_dummy_bits0_r; reg builder_csr_bankarray_csrbank2_mmap_dummy_bits0_we = 1'd0; wire [7:0] builder_csr_bankarray_csrbank2_mmap_dummy_bits0_w; wire builder_csr_bankarray_csrbank2_sel; wire [13:0] builder_csr_bankarray_interface3_bank_bus_adr; wire builder_csr_bankarray_interface3_bank_bus_we; wire [31:0] builder_csr_bankarray_interface3_bank_bus_dat_w; reg [31:0] builder_csr_bankarray_interface3_bank_bus_dat_r = 32'd0; reg builder_csr_bankarray_csrbank3_clk_divisor0_re = 1'd0; wire [7:0] builder_csr_bankarray_csrbank3_clk_divisor0_r; reg builder_csr_bankarray_csrbank3_clk_divisor0_we = 1'd0; wire [7:0] builder_csr_bankarray_csrbank3_clk_divisor0_w; wire builder_csr_bankarray_csrbank3_sel; wire [13:0] builder_csr_bankarray_interface4_bank_bus_adr; wire builder_csr_bankarray_interface4_bank_bus_we; wire [31:0] builder_csr_bankarray_interface4_bank_bus_dat_w; reg [31:0] builder_csr_bankarray_interface4_bank_bus_dat_r = 32'd0; reg builder_csr_bankarray_csrbank4_load0_re = 1'd0; wire [31:0] builder_csr_bankarray_csrbank4_load0_r; reg builder_csr_bankarray_csrbank4_load0_we = 1'd0; wire [31:0] builder_csr_bankarray_csrbank4_load0_w; reg builder_csr_bankarray_csrbank4_reload0_re = 1'd0; wire [31:0] builder_csr_bankarray_csrbank4_reload0_r; reg builder_csr_bankarray_csrbank4_reload0_we = 1'd0; wire [31:0] builder_csr_bankarray_csrbank4_reload0_w; reg builder_csr_bankarray_csrbank4_en0_re = 1'd0; wire builder_csr_bankarray_csrbank4_en0_r; reg builder_csr_bankarray_csrbank4_en0_we = 1'd0; wire builder_csr_bankarray_csrbank4_en0_w; reg builder_csr_bankarray_csrbank4_update_value0_re = 1'd0; wire builder_csr_bankarray_csrbank4_update_value0_r; reg builder_csr_bankarray_csrbank4_update_value0_we = 1'd0; wire builder_csr_bankarray_csrbank4_update_value0_w; reg builder_csr_bankarray_csrbank4_value_re = 1'd0; wire [31:0] builder_csr_bankarray_csrbank4_value_r; reg builder_csr_bankarray_csrbank4_value_we = 1'd0; wire [31:0] builder_csr_bankarray_csrbank4_value_w; reg builder_csr_bankarray_csrbank4_ev_status_re = 1'd0; wire builder_csr_bankarray_csrbank4_ev_status_r; reg builder_csr_bankarray_csrbank4_ev_status_we = 1'd0; wire builder_csr_bankarray_csrbank4_ev_status_w; reg builder_csr_bankarray_csrbank4_ev_pending_re = 1'd0; wire builder_csr_bankarray_csrbank4_ev_pending_r; reg builder_csr_bankarray_csrbank4_ev_pending_we = 1'd0; wire builder_csr_bankarray_csrbank4_ev_pending_w; reg builder_csr_bankarray_csrbank4_ev_enable0_re = 1'd0; wire builder_csr_bankarray_csrbank4_ev_enable0_r; reg builder_csr_bankarray_csrbank4_ev_enable0_we = 1'd0; wire builder_csr_bankarray_csrbank4_ev_enable0_w; wire builder_csr_bankarray_csrbank4_sel; wire [13:0] builder_csr_bankarray_interface5_bank_bus_adr; wire builder_csr_bankarray_interface5_bank_bus_we; wire [31:0] builder_csr_bankarray_interface5_bank_bus_dat_w; reg [31:0] builder_csr_bankarray_interface5_bank_bus_dat_r = 32'd0; reg builder_csr_bankarray_csrbank5_txfull_re = 1'd0; wire builder_csr_bankarray_csrbank5_txfull_r; reg builder_csr_bankarray_csrbank5_txfull_we = 1'd0; wire builder_csr_bankarray_csrbank5_txfull_w; reg builder_csr_bankarray_csrbank5_rxempty_re = 1'd0; wire builder_csr_bankarray_csrbank5_rxempty_r; reg builder_csr_bankarray_csrbank5_rxempty_we = 1'd0; wire builder_csr_bankarray_csrbank5_rxempty_w; reg builder_csr_bankarray_csrbank5_ev_status_re = 1'd0; wire [1:0] builder_csr_bankarray_csrbank5_ev_status_r; reg builder_csr_bankarray_csrbank5_ev_status_we = 1'd0; wire [1:0] builder_csr_bankarray_csrbank5_ev_status_w; reg builder_csr_bankarray_csrbank5_ev_pending_re = 1'd0; wire [1:0] builder_csr_bankarray_csrbank5_ev_pending_r; reg builder_csr_bankarray_csrbank5_ev_pending_we = 1'd0; wire [1:0] builder_csr_bankarray_csrbank5_ev_pending_w; reg builder_csr_bankarray_csrbank5_ev_enable0_re = 1'd0; wire [1:0] builder_csr_bankarray_csrbank5_ev_enable0_r; reg builder_csr_bankarray_csrbank5_ev_enable0_we = 1'd0; wire [1:0] builder_csr_bankarray_csrbank5_ev_enable0_w; reg builder_csr_bankarray_csrbank5_txempty_re = 1'd0; wire builder_csr_bankarray_csrbank5_txempty_r; reg builder_csr_bankarray_csrbank5_txempty_we = 1'd0; wire builder_csr_bankarray_csrbank5_txempty_w; reg builder_csr_bankarray_csrbank5_rxfull_re = 1'd0; wire builder_csr_bankarray_csrbank5_rxfull_r; reg builder_csr_bankarray_csrbank5_rxfull_we = 1'd0; wire builder_csr_bankarray_csrbank5_rxfull_w; wire builder_csr_bankarray_csrbank5_sel; wire [13:0] builder_csr_interconnect_adr; wire builder_csr_interconnect_we; wire [31:0] builder_csr_interconnect_dat_w; wire [31:0] builder_csr_interconnect_dat_r; reg builder_state = 1'd0; reg builder_next_state = 1'd0; reg [29:0] builder_array_muxed0 = 30'd0; reg [31:0] builder_array_muxed1 = 32'd0; reg [3:0] builder_array_muxed2 = 4'd0; reg builder_array_muxed3 = 1'd0; reg builder_array_muxed4 = 1'd0; reg builder_array_muxed5 = 1'd0; reg [2:0] builder_array_muxed6 = 3'd0; reg [1:0] builder_array_muxed7 = 2'd0; reg builder_impl_regs0 = 1'd0; reg builder_impl_regs1 = 1'd0; wire builder_impl_rst1; wire builder_impl; assign main_serv_reset = (main_soc_rst | main_cpu_rst); assign main_rst = main_soc_rst; assign main_bus_error = builder_error; assign main_bus_errors_status = main_bus_errors; assign main_serv_ibus_stb = main_serv_ibus_cyc; assign main_serv_ibus_sel = 4'd15; assign main_serv_dbus_stb = main_serv_dbus_cyc; always @(*) begin main_tx_count_rs232phytx_next_value0 <= 4'd0; main_tx_count_rs232phytx_next_value_ce0 <= 1'd0; main_serial_tx_rs232phytx_next_value1 <= 1'd0; main_serial_tx_rs232phytx_next_value_ce1 <= 1'd0; main_tx_sink_ready <= 1'd0; main_tx_data_rs232phytx_next_value2 <= 8'd0; main_tx_data_rs232phytx_next_value_ce2 <= 1'd0; main_tx_enable <= 1'd0; builder_rs232phytx_next_state <= 1'd0; builder_rs232phytx_next_state <= builder_rs232phytx_state; case (builder_rs232phytx_state) 1'd1: begin main_tx_enable <= 1'd1; if (main_tx_tick) begin main_serial_tx_rs232phytx_next_value1 <= main_tx_data; main_serial_tx_rs232phytx_next_value_ce1 <= 1'd1; main_tx_count_rs232phytx_next_value0 <= (main_tx_count + 1'd1); main_tx_count_rs232phytx_next_value_ce0 <= 1'd1; main_tx_data_rs232phytx_next_value2 <= {1'd1, main_tx_data[7:1]}; main_tx_data_rs232phytx_next_value_ce2 <= 1'd1; if ((main_tx_count == 4'd9)) begin main_tx_sink_ready <= 1'd1; builder_rs232phytx_next_state <= 1'd0; end end end default: begin main_tx_count_rs232phytx_next_value0 <= 1'd0; main_tx_count_rs232phytx_next_value_ce0 <= 1'd1; main_serial_tx_rs232phytx_next_value1 <= 1'd1; main_serial_tx_rs232phytx_next_value_ce1 <= 1'd1; if (main_tx_sink_valid) begin main_serial_tx_rs232phytx_next_value1 <= 1'd0; main_serial_tx_rs232phytx_next_value_ce1 <= 1'd1; main_tx_data_rs232phytx_next_value2 <= main_tx_sink_payload_data; main_tx_data_rs232phytx_next_value_ce2 <= 1'd1; builder_rs232phytx_next_state <= 1'd1; end end endcase end always @(*) begin builder_rs232phyrx_next_state <= 1'd0; main_rx_count_rs232phyrx_next_value0 <= 4'd0; main_rx_count_rs232phyrx_next_value_ce0 <= 1'd0; main_rx_source_valid <= 1'd0; main_rx_data_rs232phyrx_next_value1 <= 8'd0; main_rx_data_rs232phyrx_next_value_ce1 <= 1'd0; main_rx_source_payload_data <= 8'd0; main_rx_enable <= 1'd0; builder_rs232phyrx_next_state <= builder_rs232phyrx_state; case (builder_rs232phyrx_state) 1'd1: begin main_rx_enable <= 1'd1; if (main_rx_tick) begin main_rx_count_rs232phyrx_next_value0 <= (main_rx_count + 1'd1); main_rx_count_rs232phyrx_next_value_ce0 <= 1'd1; main_rx_data_rs232phyrx_next_value1 <= {main_rx_rx, main_rx_data[7:1]}; main_rx_data_rs232phyrx_next_value_ce1 <= 1'd1; if ((main_rx_count == 4'd9)) begin main_rx_source_valid <= (main_rx_rx == 1'd1); main_rx_source_payload_data <= main_rx_data; builder_rs232phyrx_next_state <= 1'd0; end end end default: begin main_rx_count_rs232phyrx_next_value0 <= 1'd0; main_rx_count_rs232phyrx_next_value_ce0 <= 1'd1; if (((main_rx_rx == 1'd0) & (main_rx_rx_d == 1'd1))) begin builder_rs232phyrx_next_state <= 1'd1; end end endcase end assign main_uart_uart_sink_valid = main_rx_source_valid; assign main_rx_source_ready = main_uart_uart_sink_ready; assign main_uart_uart_sink_first = main_rx_source_first; assign main_uart_uart_sink_last = main_rx_source_last; assign main_uart_uart_sink_payload_data = main_rx_source_payload_data; assign main_tx_sink_valid = main_uart_uart_source_valid; assign main_uart_uart_source_ready = main_tx_sink_ready; assign main_tx_sink_first = main_uart_uart_source_first; assign main_tx_sink_last = main_uart_uart_source_last; assign main_tx_sink_payload_data = main_uart_uart_source_payload_data; assign main_uart_tx_fifo_sink_valid = main_uart_rxtx_re; assign main_uart_tx_fifo_sink_payload_data = main_uart_rxtx_r; assign main_uart_uart_source_valid = main_uart_tx_fifo_source_valid; assign main_uart_tx_fifo_source_ready = main_uart_uart_source_ready; assign main_uart_uart_source_first = main_uart_tx_fifo_source_first; assign main_uart_uart_source_last = main_uart_tx_fifo_source_last; assign main_uart_uart_source_payload_data = main_uart_tx_fifo_source_payload_data; assign main_uart_txfull_status = (~main_uart_tx_fifo_sink_ready); assign main_uart_txempty_status = (~main_uart_tx_fifo_source_valid); assign main_uart_tx_trigger = main_uart_tx_fifo_sink_ready; assign main_uart_rx_fifo_sink_valid = main_uart_uart_sink_valid; assign main_uart_uart_sink_ready = main_uart_rx_fifo_sink_ready; assign main_uart_rx_fifo_sink_first = main_uart_uart_sink_first; assign main_uart_rx_fifo_sink_last = main_uart_uart_sink_last; assign main_uart_rx_fifo_sink_payload_data = main_uart_uart_sink_payload_data; assign main_uart_rxtx_w = main_uart_rx_fifo_source_payload_data; assign main_uart_rx_fifo_source_ready = (main_uart_rx_clear | (1'd0 & main_uart_rxtx_we)); assign main_uart_rxempty_status = (~main_uart_rx_fifo_source_valid); assign main_uart_rxfull_status = (~main_uart_rx_fifo_sink_ready); assign main_uart_rx_trigger = main_uart_rx_fifo_source_valid; assign main_uart_tx0 = main_uart_tx_status; assign main_uart_tx1 = main_uart_tx_pending; always @(*) begin main_uart_tx_clear <= 1'd0; if ((main_uart_pending_re & main_uart_pending_r[0])) begin main_uart_tx_clear <= 1'd1; end end assign main_uart_rx0 = main_uart_rx_status; assign main_uart_rx1 = main_uart_rx_pending; always @(*) begin main_uart_rx_clear <= 1'd0; if ((main_uart_pending_re & main_uart_pending_r[1])) begin main_uart_rx_clear <= 1'd1; end end assign main_uart_irq = ((main_uart_pending_status[0] & main_uart_enable_storage[0]) | (main_uart_pending_status[1] & main_uart_enable_storage[1])); assign main_uart_tx_status = main_uart_tx_trigger; assign main_uart_rx_status = main_uart_rx_trigger; assign main_uart_tx_fifo_syncfifo_din = {main_uart_tx_fifo_fifo_in_last, main_uart_tx_fifo_fifo_in_first, main_uart_tx_fifo_fifo_in_payload_data}; assign {main_uart_tx_fifo_fifo_out_last, main_uart_tx_fifo_fifo_out_first, main_uart_tx_fifo_fifo_out_payload_data} = main_uart_tx_fifo_syncfifo_dout; assign main_uart_tx_fifo_sink_ready = main_uart_tx_fifo_syncfifo_writable; assign main_uart_tx_fifo_syncfifo_we = main_uart_tx_fifo_sink_valid; assign main_uart_tx_fifo_fifo_in_first = main_uart_tx_fifo_sink_first; assign main_uart_tx_fifo_fifo_in_last = main_uart_tx_fifo_sink_last; assign main_uart_tx_fifo_fifo_in_payload_data = main_uart_tx_fifo_sink_payload_data; assign main_uart_tx_fifo_source_valid = main_uart_tx_fifo_readable; assign main_uart_tx_fifo_source_first = main_uart_tx_fifo_fifo_out_first; assign main_uart_tx_fifo_source_last = main_uart_tx_fifo_fifo_out_last; assign main_uart_tx_fifo_source_payload_data = main_uart_tx_fifo_fifo_out_payload_data; assign main_uart_tx_fifo_re = main_uart_tx_fifo_source_ready; assign main_uart_tx_fifo_syncfifo_re = (main_uart_tx_fifo_syncfifo_readable & ((~main_uart_tx_fifo_readable) | main_uart_tx_fifo_re)); assign main_uart_tx_fifo_level1 = (main_uart_tx_fifo_level0 + main_uart_tx_fifo_readable); always @(*) begin main_uart_tx_fifo_wrport_adr <= 4'd0; if (main_uart_tx_fifo_replace) begin main_uart_tx_fifo_wrport_adr <= (main_uart_tx_fifo_produce - 1'd1); end else begin main_uart_tx_fifo_wrport_adr <= main_uart_tx_fifo_produce; end end assign main_uart_tx_fifo_wrport_dat_w = main_uart_tx_fifo_syncfifo_din; assign main_uart_tx_fifo_wrport_we = (main_uart_tx_fifo_syncfifo_we & (main_uart_tx_fifo_syncfifo_writable | main_uart_tx_fifo_replace)); assign main_uart_tx_fifo_do_read = (main_uart_tx_fifo_syncfifo_readable & main_uart_tx_fifo_syncfifo_re); assign main_uart_tx_fifo_rdport_adr = main_uart_tx_fifo_consume; assign main_uart_tx_fifo_syncfifo_dout = main_uart_tx_fifo_rdport_dat_r; assign main_uart_tx_fifo_rdport_re = main_uart_tx_fifo_do_read; assign main_uart_tx_fifo_syncfifo_writable = (main_uart_tx_fifo_level0 != 5'd16); assign main_uart_tx_fifo_syncfifo_readable = (main_uart_tx_fifo_level0 != 1'd0); assign main_uart_rx_fifo_syncfifo_din = {main_uart_rx_fifo_fifo_in_last, main_uart_rx_fifo_fifo_in_first, main_uart_rx_fifo_fifo_in_payload_data}; assign {main_uart_rx_fifo_fifo_out_last, main_uart_rx_fifo_fifo_out_first, main_uart_rx_fifo_fifo_out_payload_data} = main_uart_rx_fifo_syncfifo_dout; assign main_uart_rx_fifo_sink_ready = main_uart_rx_fifo_syncfifo_writable; assign main_uart_rx_fifo_syncfifo_we = main_uart_rx_fifo_sink_valid; assign main_uart_rx_fifo_fifo_in_first = main_uart_rx_fifo_sink_first; assign main_uart_rx_fifo_fifo_in_last = main_uart_rx_fifo_sink_last; assign main_uart_rx_fifo_fifo_in_payload_data = main_uart_rx_fifo_sink_payload_data; assign main_uart_rx_fifo_source_valid = main_uart_rx_fifo_readable; assign main_uart_rx_fifo_source_first = main_uart_rx_fifo_fifo_out_first; assign main_uart_rx_fifo_source_last = main_uart_rx_fifo_fifo_out_last; assign main_uart_rx_fifo_source_payload_data = main_uart_rx_fifo_fifo_out_payload_data; assign main_uart_rx_fifo_re = main_uart_rx_fifo_source_ready; assign main_uart_rx_fifo_syncfifo_re = (main_uart_rx_fifo_syncfifo_readable & ((~main_uart_rx_fifo_readable) | main_uart_rx_fifo_re)); assign main_uart_rx_fifo_level1 = (main_uart_rx_fifo_level0 + main_uart_rx_fifo_readable); always @(*) begin main_uart_rx_fifo_wrport_adr <= 4'd0; if (main_uart_rx_fifo_replace) begin main_uart_rx_fifo_wrport_adr <= (main_uart_rx_fifo_produce - 1'd1); end else begin main_uart_rx_fifo_wrport_adr <= main_uart_rx_fifo_produce; end end assign main_uart_rx_fifo_wrport_dat_w = main_uart_rx_fifo_syncfifo_din; assign main_uart_rx_fifo_wrport_we = (main_uart_rx_fifo_syncfifo_we & (main_uart_rx_fifo_syncfifo_writable | main_uart_rx_fifo_replace)); assign main_uart_rx_fifo_do_read = (main_uart_rx_fifo_syncfifo_readable & main_uart_rx_fifo_syncfifo_re); assign main_uart_rx_fifo_rdport_adr = main_uart_rx_fifo_consume; assign main_uart_rx_fifo_syncfifo_dout = main_uart_rx_fifo_rdport_dat_r; assign main_uart_rx_fifo_rdport_re = main_uart_rx_fifo_do_read; assign main_uart_rx_fifo_syncfifo_writable = (main_uart_rx_fifo_level0 != 5'd16); assign main_uart_rx_fifo_syncfifo_readable = (main_uart_rx_fifo_level0 != 1'd0); assign main_timer_zero_trigger = (main_timer_value == 1'd0); assign main_timer_zero0 = main_timer_zero_status; assign main_timer_zero1 = main_timer_zero_pending; always @(*) begin main_timer_zero_clear <= 1'd0; if ((main_timer_pending_re & main_timer_pending_r)) begin main_timer_zero_clear <= 1'd1; end end assign main_timer_irq = (main_timer_pending_status & main_timer_enable_storage); assign main_timer_zero_status = main_timer_zero_trigger; assign por_clk = sys_clk; assign main_por_done = (main_por_count == 1'd0); assign main_reset = (~user_btn_n); assign main_clkin = clk12; assign sys_clk = main_clkout; assign main_datain0 = main_bus_dat_w[15:0]; always @(*) begin main_maskwren0 <= 4'd0; main_maskwren0[0] <= main_bus_sel[0]; main_maskwren0[1] <= main_bus_sel[0]; main_maskwren0[2] <= main_bus_sel[1]; main_maskwren0[3] <= main_bus_sel[1]; end assign main_datain1 = main_bus_dat_w[31:16]; always @(*) begin main_maskwren1 <= 4'd0; main_maskwren1[0] <= main_bus_sel[2]; main_maskwren1[1] <= main_bus_sel[2]; main_maskwren1[2] <= main_bus_sel[3]; main_maskwren1[3] <= main_bus_sel[3]; end assign main_datain2 = main_bus_dat_w[15:0]; always @(*) begin main_maskwren2 <= 4'd0; main_maskwren2[0] <= main_bus_sel[0]; main_maskwren2[1] <= main_bus_sel[0]; main_maskwren2[2] <= main_bus_sel[1]; main_maskwren2[3] <= main_bus_sel[1]; end assign main_datain3 = main_bus_dat_w[31:16]; always @(*) begin main_bus_dat_r <= 32'd0; main_wren3 <= 1'd0; main_wren2 <= 1'd0; main_wren1 <= 1'd0; main_wren0 <= 1'd0; if ((main_bus_adr[15:14] == 1'd0)) begin main_wren0 <= ((main_bus_we & main_bus_stb) & main_bus_cyc); main_bus_dat_r[15:0] <= main_dataout0; end if ((main_bus_adr[15:14] == 1'd0)) begin main_wren1 <= ((main_bus_we & main_bus_stb) & main_bus_cyc); main_bus_dat_r[31:16] <= main_dataout1; end if ((main_bus_adr[15:14] == 1'd1)) begin main_wren2 <= ((main_bus_we & main_bus_stb) & main_bus_cyc); main_bus_dat_r[15:0] <= main_dataout2; end if ((main_bus_adr[15:14] == 1'd1)) begin main_wren3 <= ((main_bus_we & main_bus_stb) & main_bus_cyc); main_bus_dat_r[31:16] <= main_dataout3; end end always @(*) begin main_maskwren3 <= 4'd0; main_maskwren3[0] <= main_bus_sel[2]; main_maskwren3[1] <= main_bus_sel[2]; main_maskwren3[2] <= main_bus_sel[3]; main_maskwren3[3] <= main_bus_sel[3]; end assign main_litespisdrphycore_div = main_litespisdrphycore_spi_clk_divisor; assign main_litespisdrphycore_sample_cnt = 1'd1; assign main_litespisdrphycore_update_cnt = 1'd1; assign main_litespisdrphycore_wait = main_litespisdrphycore_cs; assign main_litespisdrphycore_cs_enable = main_litespisdrphycore_done; assign spiflash_cs_n = (~main_litespisdrphycore_cs_enable); assign main_litespisdrphycore_dq_oe = main_litespisdrphycore_sink_payload_mask; always @(*) begin main_litespisdrphycore_dq_o <= 1'd0; case (main_litespisdrphycore_sink_payload_width) 1'd1: begin main_litespisdrphycore_dq_o <= main_litespisdrphycore_sr_out[31]; end 2'd2: begin main_litespisdrphycore_dq_o <= main_litespisdrphycore_sr_out[31:30]; end 3'd4: begin main_litespisdrphycore_dq_o <= main_litespisdrphycore_sr_out[31:28]; end 4'd8: begin main_litespisdrphycore_dq_o <= main_litespisdrphycore_sr_out[31:24]; end endcase end assign main_litespisdrphycore_source_payload_data = main_litespisdrphycore_sr_in; assign main_litespisdrphycore_spi_clk_divisor = main_litespisdrphycore_storage; assign main_litespisdrphycore_posedge = ((main_litespisdrphycore_en & (~main_litespisdrphycore_clk)) & (main_litespisdrphycore_cnt == main_litespisdrphycore_div)); assign main_litespisdrphycore_negedge = ((main_litespisdrphycore_en & main_litespisdrphycore_clk) & (main_litespisdrphycore_cnt == main_litespisdrphycore_div)); assign main_litespisdrphycore_sample = (main_litespisdrphycore_cnt == main_litespisdrphycore_sample_cnt); assign main_litespisdrphycore_update = (main_litespisdrphycore_cnt == main_litespisdrphycore_update_cnt); assign main_litespisdrphycore_done = (main_litespisdrphycore_count == 1'd0); always @(*) begin main_litespisdrphycore_source_last <= 1'd0; main_litespisdrphycore_sr_out_load <= 1'd0; builder_litespiphy_next_state <= 2'd0; main_litespisdrphycore_sr_out_shift <= 1'd0; main_litespisdrphycore_sink_ready <= 1'd0; main_litespisdrphycore_sr_cnt_litespiphy_next_value <= 8'd0; main_litespisdrphycore_sr_in_shift <= 1'd0; main_litespisdrphycore_sr_cnt_litespiphy_next_value_ce <= 1'd0; main_litespisdrphycore_en <= 1'd0; main_litespisdrphycore_source_valid <= 1'd0; builder_litespiphy_next_state <= builder_litespiphy_state; case (builder_litespiphy_state) 1'd1: begin main_litespisdrphycore_en <= 1'd1; if (main_litespisdrphycore_posedge_reg2) begin main_litespisdrphycore_sr_in_shift <= 1'd1; end if (main_litespisdrphycore_negedge) begin main_litespisdrphycore_sr_out_shift <= 1'd1; end if (main_litespisdrphycore_negedge) begin main_litespisdrphycore_sr_cnt_litespiphy_next_value <= (main_litespisdrphycore_sr_cnt - main_litespisdrphycore_sink_payload_width); main_litespisdrphycore_sr_cnt_litespiphy_next_value_ce <= 1'd1; if ((main_litespisdrphycore_sr_cnt == 1'd0)) begin builder_litespiphy_next_state <= 2'd2; end end end 2'd2: begin if (((main_litespisdrphycore_spi_clk_divisor > 1'd0) | main_litespisdrphycore_posedge_reg2)) begin main_litespisdrphycore_sink_ready <= 1'd1; main_litespisdrphycore_sr_in_shift <= (main_litespisdrphycore_spi_clk_divisor == 1'd0); builder_litespiphy_next_state <= 2'd3; end end 2'd3: begin main_litespisdrphycore_source_valid <= 1'd1; main_litespisdrphycore_source_last <= 1'd1; if (main_litespisdrphycore_source_ready) begin builder_litespiphy_next_state <= 1'd0; end end default: begin if ((main_litespisdrphycore_cs_enable & main_litespisdrphycore_sink_valid)) begin main_litespisdrphycore_sr_cnt_litespiphy_next_value <= (main_litespisdrphycore_sink_payload_len - main_litespisdrphycore_sink_payload_width); main_litespisdrphycore_sr_cnt_litespiphy_next_value_ce <= 1'd1; main_litespisdrphycore_sr_out_load <= 1'd1; builder_litespiphy_next_state <= 1'd1; end end endcase end assign main_litespisdrphycore_cs = main_cs; assign main_litespimmap_sink_valid = main_user_port_source_valid; assign main_user_port_source_ready = main_litespimmap_sink_ready; assign main_litespimmap_sink_first = main_user_port_source_first; assign main_litespimmap_sink_last = main_user_port_source_last; assign main_litespimmap_sink_payload_data = main_user_port_source_payload_data; assign main_user_port_sink_valid = main_litespimmap_source_valid; assign main_litespimmap_source_ready = main_user_port_sink_ready; assign main_user_port_sink_first = main_litespimmap_source_first; assign main_user_port_sink_last = main_litespimmap_source_last; assign main_user_port_sink_payload_data = main_litespimmap_source_payload_data; assign main_user_port_sink_payload_len = main_litespimmap_source_payload_len; assign main_user_port_sink_payload_width = main_litespimmap_source_payload_width; assign main_user_port_sink_payload_mask = main_litespimmap_source_payload_mask; assign main_litespisdrphycore_sink_valid = main_source_valid; assign main_source_ready = main_litespisdrphycore_sink_ready; assign main_litespisdrphycore_sink_first = main_source_first; assign main_litespisdrphycore_sink_last = main_source_last; assign main_litespisdrphycore_sink_payload_data = main_source_payload_data; assign main_litespisdrphycore_sink_payload_len = main_source_payload_len; assign main_litespisdrphycore_sink_payload_width = main_source_payload_width; assign main_litespisdrphycore_sink_payload_mask = main_source_payload_mask; assign main_sink_valid = main_litespisdrphycore_source_valid; assign main_litespisdrphycore_source_ready = main_sink_ready; assign main_sink_first = main_litespisdrphycore_source_first; assign main_sink_last = main_litespisdrphycore_source_last; assign main_sink_payload_data = main_litespisdrphycore_source_payload_data; assign main_internal_port_sink_valid = main_user_port_sink_valid; assign main_user_port_sink_ready = main_internal_port_sink_ready; assign main_internal_port_sink_first = main_user_port_sink_first; assign main_internal_port_sink_last = main_user_port_sink_last; assign main_internal_port_sink_payload_data = main_user_port_sink_payload_data; assign main_internal_port_sink_payload_len = main_user_port_sink_payload_len; assign main_internal_port_sink_payload_width = main_user_port_sink_payload_width; assign main_internal_port_sink_payload_mask = main_user_port_sink_payload_mask; assign main_user_port_source_valid = main_internal_port_source_valid; assign main_internal_port_source_ready = main_user_port_source_ready; assign main_user_port_source_first = main_internal_port_source_first; assign main_user_port_source_last = main_internal_port_source_last; assign main_user_port_source_payload_data = main_internal_port_source_payload_data; assign main_request = main_litespimmap_cs; assign builder_litespi_tx_mux_sink_valid = main_internal_port_sink_valid; assign main_internal_port_sink_ready = builder_litespi_tx_mux_sink_ready; assign builder_litespi_tx_mux_sink_first = main_internal_port_sink_first; assign builder_litespi_tx_mux_sink_last = main_internal_port_sink_last; assign builder_litespi_tx_mux_sink_payload_data = main_internal_port_sink_payload_data; assign builder_litespi_tx_mux_sink_payload_len = main_internal_port_sink_payload_len; assign builder_litespi_tx_mux_sink_payload_width = main_internal_port_sink_payload_width; assign builder_litespi_tx_mux_sink_payload_mask = main_internal_port_sink_payload_mask; assign main_internal_port_source_valid = builder_litespi_rx_demux_source_valid; assign builder_litespi_rx_demux_source_ready = main_internal_port_source_ready; assign main_internal_port_source_first = builder_litespi_rx_demux_source_first; assign main_internal_port_source_last = builder_litespi_rx_demux_source_last; assign main_internal_port_source_payload_data = builder_litespi_rx_demux_source_payload_data; assign builder_litespi_request = {main_request}; assign main_source_valid = builder_litespi_tx_mux_source_valid; assign builder_litespi_tx_mux_source_ready = main_source_ready; assign main_source_first = builder_litespi_tx_mux_source_first; assign main_source_last = builder_litespi_tx_mux_source_last; assign main_source_payload_data = builder_litespi_tx_mux_source_payload_data; assign main_source_payload_len = builder_litespi_tx_mux_source_payload_len; assign main_source_payload_width = builder_litespi_tx_mux_source_payload_width; assign main_source_payload_mask = builder_litespi_tx_mux_source_payload_mask; assign builder_litespi_tx_mux_sel = builder_litespi_grant; assign builder_litespi_rx_demux_sink_valid = main_sink_valid; assign main_sink_ready = builder_litespi_rx_demux_sink_ready; assign builder_litespi_rx_demux_sink_first = main_sink_first; assign builder_litespi_rx_demux_sink_last = main_sink_last; assign builder_litespi_rx_demux_sink_payload_data = main_sink_payload_data; assign builder_litespi_rx_demux_sel = builder_litespi_grant; always @(*) begin main_cs <= 1'd0; case (builder_litespi_grant) 1'd0: begin main_cs <= main_litespimmap_cs; end endcase end assign builder_litespi_grant = 1'd0; always @(*) begin builder_litespi_tx_mux_source_valid <= 1'd0; builder_litespi_tx_mux_source_first <= 1'd0; builder_litespi_tx_mux_source_last <= 1'd0; builder_litespi_tx_mux_source_payload_data <= 32'd0; builder_litespi_tx_mux_source_payload_len <= 6'd0; builder_litespi_tx_mux_source_payload_width <= 4'd0; builder_litespi_tx_mux_source_payload_mask <= 8'd0; builder_litespi_tx_mux_sink_ready <= 1'd0; case (builder_litespi_tx_mux_sel) 1'd0: begin builder_litespi_tx_mux_source_valid <= builder_litespi_tx_mux_sink_valid; builder_litespi_tx_mux_sink_ready <= builder_litespi_tx_mux_source_ready; builder_litespi_tx_mux_source_first <= builder_litespi_tx_mux_sink_first; builder_litespi_tx_mux_source_last <= builder_litespi_tx_mux_sink_last; builder_litespi_tx_mux_source_payload_data <= builder_litespi_tx_mux_sink_payload_data; builder_litespi_tx_mux_source_payload_len <= builder_litespi_tx_mux_sink_payload_len; builder_litespi_tx_mux_source_payload_width <= builder_litespi_tx_mux_sink_payload_width; builder_litespi_tx_mux_source_payload_mask <= builder_litespi_tx_mux_sink_payload_mask; end endcase end always @(*) begin builder_litespi_rx_demux_source_payload_data <= 32'd0; builder_litespi_rx_demux_source_first <= 1'd0; builder_litespi_rx_demux_source_last <= 1'd0; builder_litespi_rx_demux_sink_ready <= 1'd0; builder_litespi_rx_demux_source_valid <= 1'd0; case (builder_litespi_rx_demux_sel) 1'd0: begin builder_litespi_rx_demux_source_valid <= builder_litespi_rx_demux_sink_valid; builder_litespi_rx_demux_sink_ready <= builder_litespi_rx_demux_source_ready; builder_litespi_rx_demux_source_first <= builder_litespi_rx_demux_sink_first; builder_litespi_rx_demux_source_last <= builder_litespi_rx_demux_sink_last; builder_litespi_rx_demux_source_payload_data <= builder_litespi_rx_demux_sink_payload_data; end endcase end assign main_litespimmap_spi_dummy_bits = main_litespimmap_storage; assign main_litespimmap_done = (main_litespimmap_count == 1'd0); always @(*) begin main_litespimmap_bus_ack <= 1'd0; main_litespimmap_cs <= 1'd0; main_litespimmap_wait <= 1'd0; builder_litespi_next_state <= 4'd0; main_litespimmap_source_valid <= 1'd0; main_litespimmap_burst_cs_litespi_next_value0 <= 1'd0; main_litespimmap_burst_cs_litespi_next_value_ce0 <= 1'd0; main_litespimmap_source_last <= 1'd0; main_litespimmap_source_payload_data <= 32'd0; main_litespimmap_source_payload_len <= 6'd0; main_litespimmap_source_payload_width <= 4'd0; main_litespimmap_burst_adr_litespi_next_value1 <= 30'd0; main_litespimmap_source_payload_mask <= 8'd0; main_litespimmap_burst_adr_litespi_next_value_ce1 <= 1'd0; main_litespimmap_sink_ready <= 1'd0; main_litespimmap_bus_dat_r <= 32'd0; builder_litespi_next_state <= builder_litespi_state; case (builder_litespi_state) 1'd1: begin main_litespimmap_cs <= 1'd1; main_litespimmap_source_valid <= 1'd1; main_litespimmap_source_payload_data <= 2'd3; main_litespimmap_source_payload_len <= 4'd8; main_litespimmap_source_payload_width <= 1'd1; main_litespimmap_source_payload_mask <= 1'd1; main_litespimmap_burst_adr_litespi_next_value1 <= main_litespimmap_bus_adr; main_litespimmap_burst_adr_litespi_next_value_ce1 <= 1'd1; if (main_litespimmap_source_ready) begin builder_litespi_next_state <= 2'd2; end end 2'd2: begin main_litespimmap_cs <= 1'd1; main_litespimmap_sink_ready <= 1'd1; if (main_litespimmap_sink_valid) begin builder_litespi_next_state <= 2'd3; end end 2'd3: begin main_litespimmap_cs <= 1'd1; main_litespimmap_source_valid <= 1'd1; main_litespimmap_source_payload_width <= 1'd1; main_litespimmap_source_payload_mask <= 1'd1; main_litespimmap_source_payload_data <= {main_litespimmap_bus_adr, main_litespimmap}; main_litespimmap_source_payload_len <= 5'd24; main_litespimmap_burst_cs_litespi_next_value0 <= 1'd1; main_litespimmap_burst_cs_litespi_next_value_ce0 <= 1'd1; main_litespimmap_burst_adr_litespi_next_value1 <= main_litespimmap_bus_adr; main_litespimmap_burst_adr_litespi_next_value_ce1 <= 1'd1; if (main_litespimmap_source_ready) begin builder_litespi_next_state <= 3'd4; end end 3'd4: begin main_litespimmap_cs <= 1'd1; main_litespimmap_sink_ready <= 1'd1; if (main_litespimmap_sink_valid) begin if ((main_litespimmap_spi_dummy_bits == 1'd0)) begin builder_litespi_next_state <= 3'd7; end else begin builder_litespi_next_state <= 3'd5; end end end 3'd5: begin main_litespimmap_cs <= 1'd1; main_litespimmap_source_valid <= 1'd1; main_litespimmap_source_payload_width <= 1'd1; main_litespimmap_source_payload_mask <= 1'd1; main_litespimmap_source_payload_data <= main_litespimmap_dummy; main_litespimmap_source_payload_len <= main_litespimmap_spi_dummy_bits; main_litespimmap_burst_cs_litespi_next_value0 <= 1'd1; main_litespimmap_burst_cs_litespi_next_value_ce0 <= 1'd1; main_litespimmap_burst_adr_litespi_next_value1 <= main_litespimmap_bus_adr; main_litespimmap_burst_adr_litespi_next_value_ce1 <= 1'd1; if (main_litespimmap_source_ready) begin builder_litespi_next_state <= 3'd6; end end 3'd6: begin main_litespimmap_cs <= 1'd1; main_litespimmap_sink_ready <= 1'd1; if (main_litespimmap_sink_valid) begin builder_litespi_next_state <= 3'd7; end end 3'd7: begin main_litespimmap_cs <= 1'd1; main_litespimmap_source_valid <= 1'd1; main_litespimmap_source_last <= 1'd1; main_litespimmap_source_payload_width <= 1'd1; main_litespimmap_source_payload_len <= 6'd32; main_litespimmap_source_payload_mask <= 1'd0; if (main_litespimmap_source_ready) begin builder_litespi_next_state <= 4'd8; end end 4'd8: begin main_litespimmap_cs <= 1'd1; main_litespimmap_sink_ready <= 1'd1; main_litespimmap_bus_dat_r <= {main_litespimmap_sink_payload_data[7:0], main_litespimmap_sink_payload_data[15:8], main_litespimmap_sink_payload_data[23:16], main_litespimmap_sink_payload_data[31:24]}; if (main_litespimmap_sink_valid) begin main_litespimmap_bus_ack <= 1'd1; main_litespimmap_burst_adr_litespi_next_value1 <= (main_litespimmap_burst_adr + 1'd1); main_litespimmap_burst_adr_litespi_next_value_ce1 <= 1'd1; builder_litespi_next_state <= 1'd0; end end default: begin main_litespimmap_wait <= 1'd1; main_litespimmap_burst_cs_litespi_next_value0 <= (main_litespimmap_burst_cs & (~main_litespimmap_done)); main_litespimmap_burst_cs_litespi_next_value_ce0 <= 1'd1; main_litespimmap_cs <= main_litespimmap_burst_cs; if (((main_litespimmap_bus_cyc & main_litespimmap_bus_stb) & (~main_litespimmap_bus_we))) begin if ((main_litespimmap_burst_cs & (main_litespimmap_bus_adr == main_litespimmap_burst_adr))) begin builder_litespi_next_state <= 3'd7; end else begin main_litespimmap_cs <= 1'd0; builder_litespi_next_state <= 1'd1; end end end endcase end assign main_wait = (~main_done); always @(*) begin user_led0 <= 1'd0; user_led1 <= 1'd0; user_led2 <= 1'd0; user_led3 <= 1'd0; user_led4 <= 1'd0; if ((main_mode == 1'd1)) begin {user_led4, user_led3, user_led2, user_led1, user_led0} <= main_storage; end else begin {user_led4, user_led3, user_led2, user_led1, user_led0} <= main_chaser; end end assign main_done = (main_count == 1'd0); always @(*) begin builder_basesoc_dat_w <= 32'd0; builder_basesoc_wishbone_dat_r <= 32'd0; builder_next_state <= 1'd0; builder_basesoc_adr <= 14'd0; builder_basesoc_we <= 1'd0; builder_basesoc_wishbone_ack <= 1'd0; builder_next_state <= builder_state; case (builder_state) 1'd1: begin builder_basesoc_wishbone_ack <= 1'd1; builder_basesoc_wishbone_dat_r <= builder_basesoc_dat_r; builder_next_state <= 1'd0; end default: begin builder_basesoc_dat_w <= builder_basesoc_wishbone_dat_w; if ((builder_basesoc_wishbone_cyc & builder_basesoc_wishbone_stb)) begin builder_basesoc_adr <= builder_basesoc_wishbone_adr; builder_basesoc_we <= (builder_basesoc_wishbone_we & (builder_basesoc_wishbone_sel != 1'd0)); builder_next_state <= 1'd1; end end endcase end assign builder_shared_adr = builder_array_muxed0; assign builder_shared_dat_w = builder_array_muxed1; assign builder_shared_sel = builder_array_muxed2; assign builder_shared_cyc = builder_array_muxed3; assign builder_shared_stb = builder_array_muxed4; assign builder_shared_we = builder_array_muxed5; assign builder_shared_cti = builder_array_muxed6; assign builder_shared_bte = builder_array_muxed7; assign main_serv_ibus_dat_r = builder_shared_dat_r; assign main_serv_dbus_dat_r = builder_shared_dat_r; assign main_serv_ibus_ack = (builder_shared_ack & (builder_grant == 1'd0)); assign main_serv_dbus_ack = (builder_shared_ack & (builder_grant == 1'd1)); assign main_serv_ibus_err = (builder_shared_err & (builder_grant == 1'd0)); assign main_serv_dbus_err = (builder_shared_err & (builder_grant == 1'd1)); assign builder_request = {main_serv_dbus_cyc, main_serv_ibus_cyc}; always @(*) begin builder_slave_sel <= 3'd0; builder_slave_sel[0] <= (builder_shared_adr[29:15] == 1'd0); builder_slave_sel[1] <= (builder_shared_adr[29:22] == 8'd128); builder_slave_sel[2] <= (builder_shared_adr[29:14] == 16'd33280); end assign main_bus_adr = builder_shared_adr; assign main_bus_dat_w = builder_shared_dat_w; assign main_bus_sel = builder_shared_sel; assign main_bus_stb = builder_shared_stb; assign main_bus_we = builder_shared_we; assign main_bus_cti = builder_shared_cti; assign main_bus_bte = builder_shared_bte; assign main_litespimmap_bus_adr = builder_shared_adr; assign main_litespimmap_bus_dat_w = builder_shared_dat_w; assign main_litespimmap_bus_sel = builder_shared_sel; assign main_litespimmap_bus_stb = builder_shared_stb; assign main_litespimmap_bus_we = builder_shared_we; assign main_litespimmap_bus_cti = builder_shared_cti; assign main_litespimmap_bus_bte = builder_shared_bte; assign builder_basesoc_wishbone_adr = builder_shared_adr; assign builder_basesoc_wishbone_dat_w = builder_shared_dat_w; assign builder_basesoc_wishbone_sel = builder_shared_sel; assign builder_basesoc_wishbone_stb = builder_shared_stb; assign builder_basesoc_wishbone_we = builder_shared_we; assign builder_basesoc_wishbone_cti = builder_shared_cti; assign builder_basesoc_wishbone_bte = builder_shared_bte; assign main_bus_cyc = (builder_shared_cyc & builder_slave_sel[0]); assign main_litespimmap_bus_cyc = (builder_shared_cyc & builder_slave_sel[1]); assign builder_basesoc_wishbone_cyc = (builder_shared_cyc & builder_slave_sel[2]); assign builder_shared_err = ((main_bus_err | main_litespimmap_bus_err) | builder_basesoc_wishbone_err); assign builder_wait = ((builder_shared_stb & builder_shared_cyc) & (~builder_shared_ack)); always @(*) begin builder_shared_ack <= 1'd0; builder_shared_dat_r <= 32'd0; builder_error <= 1'd0; builder_shared_ack <= ((main_bus_ack | main_litespimmap_bus_ack) | builder_basesoc_wishbone_ack); builder_shared_dat_r <= ((({32{builder_slave_sel_r[0]}} & main_bus_dat_r) | ({32{builder_slave_sel_r[1]}} & main_litespimmap_bus_dat_r)) | ({32{builder_slave_sel_r[2]}} & builder_basesoc_wishbone_dat_r)); if (builder_done) begin builder_shared_dat_r <= 32'd4294967295; builder_shared_ack <= 1'd1; builder_error <= 1'd1; end end assign builder_done = (builder_count == 1'd0); assign builder_csr_bankarray_csrbank0_sel = (builder_csr_bankarray_interface0_bank_bus_adr[13:9] == 1'd0); assign builder_csr_bankarray_csrbank0_reset0_r = builder_csr_bankarray_interface0_bank_bus_dat_w[1:0]; always @(*) begin builder_csr_bankarray_csrbank0_reset0_re <= 1'd0; builder_csr_bankarray_csrbank0_reset0_we <= 1'd0; if ((builder_csr_bankarray_csrbank0_sel & (builder_csr_bankarray_interface0_bank_bus_adr[8:0] == 1'd0))) begin builder_csr_bankarray_csrbank0_reset0_re <= builder_csr_bankarray_interface0_bank_bus_we; builder_csr_bankarray_csrbank0_reset0_we <= (~builder_csr_bankarray_interface0_bank_bus_we); end end assign builder_csr_bankarray_csrbank0_scratch0_r = builder_csr_bankarray_interface0_bank_bus_dat_w[31:0]; always @(*) begin builder_csr_bankarray_csrbank0_scratch0_we <= 1'd0; builder_csr_bankarray_csrbank0_scratch0_re <= 1'd0; if ((builder_csr_bankarray_csrbank0_sel & (builder_csr_bankarray_interface0_bank_bus_adr[8:0] == 1'd1))) begin builder_csr_bankarray_csrbank0_scratch0_re <= builder_csr_bankarray_interface0_bank_bus_we; builder_csr_bankarray_csrbank0_scratch0_we <= (~builder_csr_bankarray_interface0_bank_bus_we); end end assign builder_csr_bankarray_csrbank0_bus_errors_r = builder_csr_bankarray_interface0_bank_bus_dat_w[31:0]; always @(*) begin builder_csr_bankarray_csrbank0_bus_errors_re <= 1'd0; builder_csr_bankarray_csrbank0_bus_errors_we <= 1'd0; if ((builder_csr_bankarray_csrbank0_sel & (builder_csr_bankarray_interface0_bank_bus_adr[8:0] == 2'd2))) begin builder_csr_bankarray_csrbank0_bus_errors_re <= builder_csr_bankarray_interface0_bank_bus_we; builder_csr_bankarray_csrbank0_bus_errors_we <= (~builder_csr_bankarray_interface0_bank_bus_we); end end always @(*) begin main_soc_rst <= 1'd0; if (main_reset_re) begin main_soc_rst <= main_reset_storage[0]; end end assign main_cpu_rst = main_reset_storage[1]; assign builder_csr_bankarray_csrbank0_reset0_w = main_reset_storage[1:0]; assign builder_csr_bankarray_csrbank0_scratch0_w = main_scratch_storage[31:0]; assign builder_csr_bankarray_csrbank0_bus_errors_w = main_bus_errors_status[31:0]; assign main_bus_errors_we = builder_csr_bankarray_csrbank0_bus_errors_we; assign builder_csr_bankarray_sel = (builder_csr_bankarray_sram_bus_adr[13:9] == 1'd1); always @(*) begin builder_csr_bankarray_sram_bus_dat_r <= 32'd0; if (builder_csr_bankarray_sel_r) begin builder_csr_bankarray_sram_bus_dat_r <= builder_csr_bankarray_dat_r; end end assign builder_csr_bankarray_adr = builder_csr_bankarray_sram_bus_adr[5:0]; assign builder_csr_bankarray_csrbank1_sel = (builder_csr_bankarray_interface1_bank_bus_adr[13:9] == 2'd2); assign builder_csr_bankarray_csrbank1_out0_r = builder_csr_bankarray_interface1_bank_bus_dat_w[4:0]; always @(*) begin builder_csr_bankarray_csrbank1_out0_we <= 1'd0; builder_csr_bankarray_csrbank1_out0_re <= 1'd0; if ((builder_csr_bankarray_csrbank1_sel & (builder_csr_bankarray_interface1_bank_bus_adr[8:0] == 1'd0))) begin builder_csr_bankarray_csrbank1_out0_re <= builder_csr_bankarray_interface1_bank_bus_we; builder_csr_bankarray_csrbank1_out0_we <= (~builder_csr_bankarray_interface1_bank_bus_we); end end assign builder_csr_bankarray_csrbank1_out0_w = main_storage[4:0]; assign builder_csr_bankarray_csrbank2_sel = (builder_csr_bankarray_interface2_bank_bus_adr[13:9] == 2'd3); assign builder_csr_bankarray_csrbank2_mmap_dummy_bits0_r = builder_csr_bankarray_interface2_bank_bus_dat_w[7:0]; always @(*) begin builder_csr_bankarray_csrbank2_mmap_dummy_bits0_we <= 1'd0; builder_csr_bankarray_csrbank2_mmap_dummy_bits0_re <= 1'd0; if ((builder_csr_bankarray_csrbank2_sel & (builder_csr_bankarray_interface2_bank_bus_adr[8:0] == 1'd0))) begin builder_csr_bankarray_csrbank2_mmap_dummy_bits0_re <= builder_csr_bankarray_interface2_bank_bus_we; builder_csr_bankarray_csrbank2_mmap_dummy_bits0_we <= (~builder_csr_bankarray_interface2_bank_bus_we); end end assign builder_csr_bankarray_csrbank2_mmap_dummy_bits0_w = main_litespimmap_storage[7:0]; assign builder_csr_bankarray_csrbank3_sel = (builder_csr_bankarray_interface3_bank_bus_adr[13:9] == 3'd4); assign builder_csr_bankarray_csrbank3_clk_divisor0_r = builder_csr_bankarray_interface3_bank_bus_dat_w[7:0]; always @(*) begin builder_csr_bankarray_csrbank3_clk_divisor0_we <= 1'd0; builder_csr_bankarray_csrbank3_clk_divisor0_re <= 1'd0; if ((builder_csr_bankarray_csrbank3_sel & (builder_csr_bankarray_interface3_bank_bus_adr[8:0] == 1'd0))) begin builder_csr_bankarray_csrbank3_clk_divisor0_re <= builder_csr_bankarray_interface3_bank_bus_we; builder_csr_bankarray_csrbank3_clk_divisor0_we <= (~builder_csr_bankarray_interface3_bank_bus_we); end end assign builder_csr_bankarray_csrbank3_clk_divisor0_w = main_litespisdrphycore_storage[7:0]; assign builder_csr_bankarray_csrbank4_sel = (builder_csr_bankarray_interface4_bank_bus_adr[13:9] == 3'd5); assign builder_csr_bankarray_csrbank4_load0_r = builder_csr_bankarray_interface4_bank_bus_dat_w[31:0]; always @(*) begin builder_csr_bankarray_csrbank4_load0_re <= 1'd0; builder_csr_bankarray_csrbank4_load0_we <= 1'd0; if ((builder_csr_bankarray_csrbank4_sel & (builder_csr_bankarray_interface4_bank_bus_adr[8:0] == 1'd0))) begin builder_csr_bankarray_csrbank4_load0_re <= builder_csr_bankarray_interface4_bank_bus_we; builder_csr_bankarray_csrbank4_load0_we <= (~builder_csr_bankarray_interface4_bank_bus_we); end end assign builder_csr_bankarray_csrbank4_reload0_r = builder_csr_bankarray_interface4_bank_bus_dat_w[31:0]; always @(*) begin builder_csr_bankarray_csrbank4_reload0_re <= 1'd0; builder_csr_bankarray_csrbank4_reload0_we <= 1'd0; if ((builder_csr_bankarray_csrbank4_sel & (builder_csr_bankarray_interface4_bank_bus_adr[8:0] == 1'd1))) begin builder_csr_bankarray_csrbank4_reload0_re <= builder_csr_bankarray_interface4_bank_bus_we; builder_csr_bankarray_csrbank4_reload0_we <= (~builder_csr_bankarray_interface4_bank_bus_we); end end assign builder_csr_bankarray_csrbank4_en0_r = builder_csr_bankarray_interface4_bank_bus_dat_w[0]; always @(*) begin builder_csr_bankarray_csrbank4_en0_we <= 1'd0; builder_csr_bankarray_csrbank4_en0_re <= 1'd0; if ((builder_csr_bankarray_csrbank4_sel & (builder_csr_bankarray_interface4_bank_bus_adr[8:0] == 2'd2))) begin builder_csr_bankarray_csrbank4_en0_re <= builder_csr_bankarray_interface4_bank_bus_we; builder_csr_bankarray_csrbank4_en0_we <= (~builder_csr_bankarray_interface4_bank_bus_we); end end assign builder_csr_bankarray_csrbank4_update_value0_r = builder_csr_bankarray_interface4_bank_bus_dat_w[0]; always @(*) begin builder_csr_bankarray_csrbank4_update_value0_re <= 1'd0; builder_csr_bankarray_csrbank4_update_value0_we <= 1'd0; if ((builder_csr_bankarray_csrbank4_sel & (builder_csr_bankarray_interface4_bank_bus_adr[8:0] == 2'd3))) begin builder_csr_bankarray_csrbank4_update_value0_re <= builder_csr_bankarray_interface4_bank_bus_we; builder_csr_bankarray_csrbank4_update_value0_we <= (~builder_csr_bankarray_interface4_bank_bus_we); end end assign builder_csr_bankarray_csrbank4_value_r = builder_csr_bankarray_interface4_bank_bus_dat_w[31:0]; always @(*) begin builder_csr_bankarray_csrbank4_value_we <= 1'd0; builder_csr_bankarray_csrbank4_value_re <= 1'd0; if ((builder_csr_bankarray_csrbank4_sel & (builder_csr_bankarray_interface4_bank_bus_adr[8:0] == 3'd4))) begin builder_csr_bankarray_csrbank4_value_re <= builder_csr_bankarray_interface4_bank_bus_we; builder_csr_bankarray_csrbank4_value_we <= (~builder_csr_bankarray_interface4_bank_bus_we); end end assign builder_csr_bankarray_csrbank4_ev_status_r = builder_csr_bankarray_interface4_bank_bus_dat_w[0]; always @(*) begin builder_csr_bankarray_csrbank4_ev_status_we <= 1'd0; builder_csr_bankarray_csrbank4_ev_status_re <= 1'd0; if ((builder_csr_bankarray_csrbank4_sel & (builder_csr_bankarray_interface4_bank_bus_adr[8:0] == 3'd5))) begin builder_csr_bankarray_csrbank4_ev_status_re <= builder_csr_bankarray_interface4_bank_bus_we; builder_csr_bankarray_csrbank4_ev_status_we <= (~builder_csr_bankarray_interface4_bank_bus_we); end end assign builder_csr_bankarray_csrbank4_ev_pending_r = builder_csr_bankarray_interface4_bank_bus_dat_w[0]; always @(*) begin builder_csr_bankarray_csrbank4_ev_pending_re <= 1'd0; builder_csr_bankarray_csrbank4_ev_pending_we <= 1'd0; if ((builder_csr_bankarray_csrbank4_sel & (builder_csr_bankarray_interface4_bank_bus_adr[8:0] == 3'd6))) begin builder_csr_bankarray_csrbank4_ev_pending_re <= builder_csr_bankarray_interface4_bank_bus_we; builder_csr_bankarray_csrbank4_ev_pending_we <= (~builder_csr_bankarray_interface4_bank_bus_we); end end assign builder_csr_bankarray_csrbank4_ev_enable0_r = builder_csr_bankarray_interface4_bank_bus_dat_w[0]; always @(*) begin builder_csr_bankarray_csrbank4_ev_enable0_re <= 1'd0; builder_csr_bankarray_csrbank4_ev_enable0_we <= 1'd0; if ((builder_csr_bankarray_csrbank4_sel & (builder_csr_bankarray_interface4_bank_bus_adr[8:0] == 3'd7))) begin builder_csr_bankarray_csrbank4_ev_enable0_re <= builder_csr_bankarray_interface4_bank_bus_we; builder_csr_bankarray_csrbank4_ev_enable0_we <= (~builder_csr_bankarray_interface4_bank_bus_we); end end assign builder_csr_bankarray_csrbank4_load0_w = main_timer_load_storage[31:0]; assign builder_csr_bankarray_csrbank4_reload0_w = main_timer_reload_storage[31:0]; assign builder_csr_bankarray_csrbank4_en0_w = main_timer_en_storage; assign builder_csr_bankarray_csrbank4_update_value0_w = main_timer_update_value_storage; assign builder_csr_bankarray_csrbank4_value_w = main_timer_value_status[31:0]; assign main_timer_value_we = builder_csr_bankarray_csrbank4_value_we; assign main_timer_status_status = main_timer_zero0; assign builder_csr_bankarray_csrbank4_ev_status_w = main_timer_status_status; assign main_timer_status_we = builder_csr_bankarray_csrbank4_ev_status_we; assign main_timer_pending_status = main_timer_zero1; assign builder_csr_bankarray_csrbank4_ev_pending_w = main_timer_pending_status; assign main_timer_pending_we = builder_csr_bankarray_csrbank4_ev_pending_we; assign main_timer_zero2 = main_timer_enable_storage; assign builder_csr_bankarray_csrbank4_ev_enable0_w = main_timer_enable_storage; assign builder_csr_bankarray_csrbank5_sel = (builder_csr_bankarray_interface5_bank_bus_adr[13:9] == 3'd6); assign main_uart_rxtx_r = builder_csr_bankarray_interface5_bank_bus_dat_w[7:0]; always @(*) begin main_uart_rxtx_re <= 1'd0; main_uart_rxtx_we <= 1'd0; if ((builder_csr_bankarray_csrbank5_sel & (builder_csr_bankarray_interface5_bank_bus_adr[8:0] == 1'd0))) begin main_uart_rxtx_re <= builder_csr_bankarray_interface5_bank_bus_we; main_uart_rxtx_we <= (~builder_csr_bankarray_interface5_bank_bus_we); end end assign builder_csr_bankarray_csrbank5_txfull_r = builder_csr_bankarray_interface5_bank_bus_dat_w[0]; always @(*) begin builder_csr_bankarray_csrbank5_txfull_we <= 1'd0; builder_csr_bankarray_csrbank5_txfull_re <= 1'd0; if ((builder_csr_bankarray_csrbank5_sel & (builder_csr_bankarray_interface5_bank_bus_adr[8:0] == 1'd1))) begin builder_csr_bankarray_csrbank5_txfull_re <= builder_csr_bankarray_interface5_bank_bus_we; builder_csr_bankarray_csrbank5_txfull_we <= (~builder_csr_bankarray_interface5_bank_bus_we); end end assign builder_csr_bankarray_csrbank5_rxempty_r = builder_csr_bankarray_interface5_bank_bus_dat_w[0]; always @(*) begin builder_csr_bankarray_csrbank5_rxempty_we <= 1'd0; builder_csr_bankarray_csrbank5_rxempty_re <= 1'd0; if ((builder_csr_bankarray_csrbank5_sel & (builder_csr_bankarray_interface5_bank_bus_adr[8:0] == 2'd2))) begin builder_csr_bankarray_csrbank5_rxempty_re <= builder_csr_bankarray_interface5_bank_bus_we; builder_csr_bankarray_csrbank5_rxempty_we <= (~builder_csr_bankarray_interface5_bank_bus_we); end end assign builder_csr_bankarray_csrbank5_ev_status_r = builder_csr_bankarray_interface5_bank_bus_dat_w[1:0]; always @(*) begin builder_csr_bankarray_csrbank5_ev_status_re <= 1'd0; builder_csr_bankarray_csrbank5_ev_status_we <= 1'd0; if ((builder_csr_bankarray_csrbank5_sel & (builder_csr_bankarray_interface5_bank_bus_adr[8:0] == 2'd3))) begin builder_csr_bankarray_csrbank5_ev_status_re <= builder_csr_bankarray_interface5_bank_bus_we; builder_csr_bankarray_csrbank5_ev_status_we <= (~builder_csr_bankarray_interface5_bank_bus_we); end end assign builder_csr_bankarray_csrbank5_ev_pending_r = builder_csr_bankarray_interface5_bank_bus_dat_w[1:0]; always @(*) begin builder_csr_bankarray_csrbank5_ev_pending_re <= 1'd0; builder_csr_bankarray_csrbank5_ev_pending_we <= 1'd0; if ((builder_csr_bankarray_csrbank5_sel & (builder_csr_bankarray_interface5_bank_bus_adr[8:0] == 3'd4))) begin builder_csr_bankarray_csrbank5_ev_pending_re <= builder_csr_bankarray_interface5_bank_bus_we; builder_csr_bankarray_csrbank5_ev_pending_we <= (~builder_csr_bankarray_interface5_bank_bus_we); end end assign builder_csr_bankarray_csrbank5_ev_enable0_r = builder_csr_bankarray_interface5_bank_bus_dat_w[1:0]; always @(*) begin builder_csr_bankarray_csrbank5_ev_enable0_we <= 1'd0; builder_csr_bankarray_csrbank5_ev_enable0_re <= 1'd0; if ((builder_csr_bankarray_csrbank5_sel & (builder_csr_bankarray_interface5_bank_bus_adr[8:0] == 3'd5))) begin builder_csr_bankarray_csrbank5_ev_enable0_re <= builder_csr_bankarray_interface5_bank_bus_we; builder_csr_bankarray_csrbank5_ev_enable0_we <= (~builder_csr_bankarray_interface5_bank_bus_we); end end assign builder_csr_bankarray_csrbank5_txempty_r = builder_csr_bankarray_interface5_bank_bus_dat_w[0]; always @(*) begin builder_csr_bankarray_csrbank5_txempty_re <= 1'd0; builder_csr_bankarray_csrbank5_txempty_we <= 1'd0; if ((builder_csr_bankarray_csrbank5_sel & (builder_csr_bankarray_interface5_bank_bus_adr[8:0] == 3'd6))) begin builder_csr_bankarray_csrbank5_txempty_re <= builder_csr_bankarray_interface5_bank_bus_we; builder_csr_bankarray_csrbank5_txempty_we <= (~builder_csr_bankarray_interface5_bank_bus_we); end end assign builder_csr_bankarray_csrbank5_rxfull_r = builder_csr_bankarray_interface5_bank_bus_dat_w[0]; always @(*) begin builder_csr_bankarray_csrbank5_rxfull_re <= 1'd0; builder_csr_bankarray_csrbank5_rxfull_we <= 1'd0; if ((builder_csr_bankarray_csrbank5_sel & (builder_csr_bankarray_interface5_bank_bus_adr[8:0] == 3'd7))) begin builder_csr_bankarray_csrbank5_rxfull_re <= builder_csr_bankarray_interface5_bank_bus_we; builder_csr_bankarray_csrbank5_rxfull_we <= (~builder_csr_bankarray_interface5_bank_bus_we); end end assign builder_csr_bankarray_csrbank5_txfull_w = main_uart_txfull_status; assign main_uart_txfull_we = builder_csr_bankarray_csrbank5_txfull_we; assign builder_csr_bankarray_csrbank5_rxempty_w = main_uart_rxempty_status; assign main_uart_rxempty_we = builder_csr_bankarray_csrbank5_rxempty_we; always @(*) begin main_uart_status_status <= 2'd0; main_uart_status_status[0] <= main_uart_tx0; main_uart_status_status[1] <= main_uart_rx0; end assign builder_csr_bankarray_csrbank5_ev_status_w = main_uart_status_status[1:0]; assign main_uart_status_we = builder_csr_bankarray_csrbank5_ev_status_we; always @(*) begin main_uart_pending_status <= 2'd0; main_uart_pending_status[0] <= main_uart_tx1; main_uart_pending_status[1] <= main_uart_rx1; end assign builder_csr_bankarray_csrbank5_ev_pending_w = main_uart_pending_status[1:0]; assign main_uart_pending_we = builder_csr_bankarray_csrbank5_ev_pending_we; assign main_uart_tx2 = main_uart_enable_storage[0]; assign main_uart_rx2 = main_uart_enable_storage[1]; assign builder_csr_bankarray_csrbank5_ev_enable0_w = main_uart_enable_storage[1:0]; assign builder_csr_bankarray_csrbank5_txempty_w = main_uart_txempty_status; assign main_uart_txempty_we = builder_csr_bankarray_csrbank5_txempty_we; assign builder_csr_bankarray_csrbank5_rxfull_w = main_uart_rxfull_status; assign main_uart_rxfull_we = builder_csr_bankarray_csrbank5_rxfull_we; assign builder_csr_interconnect_adr = builder_basesoc_adr; assign builder_csr_interconnect_we = builder_basesoc_we; assign builder_csr_interconnect_dat_w = builder_basesoc_dat_w; assign builder_basesoc_dat_r = builder_csr_interconnect_dat_r; assign builder_csr_bankarray_interface0_bank_bus_adr = builder_csr_interconnect_adr; assign builder_csr_bankarray_interface1_bank_bus_adr = builder_csr_interconnect_adr; assign builder_csr_bankarray_interface2_bank_bus_adr = builder_csr_interconnect_adr; assign builder_csr_bankarray_interface3_bank_bus_adr = builder_csr_interconnect_adr; assign builder_csr_bankarray_interface4_bank_bus_adr = builder_csr_interconnect_adr; assign builder_csr_bankarray_interface5_bank_bus_adr = builder_csr_interconnect_adr; assign builder_csr_bankarray_sram_bus_adr = builder_csr_interconnect_adr; assign builder_csr_bankarray_interface0_bank_bus_we = builder_csr_interconnect_we; assign builder_csr_bankarray_interface1_bank_bus_we = builder_csr_interconnect_we; assign builder_csr_bankarray_interface2_bank_bus_we = builder_csr_interconnect_we; assign builder_csr_bankarray_interface3_bank_bus_we = builder_csr_interconnect_we; assign builder_csr_bankarray_interface4_bank_bus_we = builder_csr_interconnect_we; assign builder_csr_bankarray_interface5_bank_bus_we = builder_csr_interconnect_we; assign builder_csr_bankarray_sram_bus_we = builder_csr_interconnect_we; assign builder_csr_bankarray_interface0_bank_bus_dat_w = builder_csr_interconnect_dat_w; assign builder_csr_bankarray_interface1_bank_bus_dat_w = builder_csr_interconnect_dat_w; assign builder_csr_bankarray_interface2_bank_bus_dat_w = builder_csr_interconnect_dat_w; assign builder_csr_bankarray_interface3_bank_bus_dat_w = builder_csr_interconnect_dat_w; assign builder_csr_bankarray_interface4_bank_bus_dat_w = builder_csr_interconnect_dat_w; assign builder_csr_bankarray_interface5_bank_bus_dat_w = builder_csr_interconnect_dat_w; assign builder_csr_bankarray_sram_bus_dat_w = builder_csr_interconnect_dat_w; assign builder_csr_interconnect_dat_r = ((((((builder_csr_bankarray_interface0_bank_bus_dat_r | builder_csr_bankarray_interface1_bank_bus_dat_r) | builder_csr_bankarray_interface2_bank_bus_dat_r) | builder_csr_bankarray_interface3_bank_bus_dat_r) | builder_csr_bankarray_interface4_bank_bus_dat_r) | builder_csr_bankarray_interface5_bank_bus_dat_r) | builder_csr_bankarray_sram_bus_dat_r); always @(*) begin builder_array_muxed0 <= 30'd0; case (builder_grant) 1'd0: begin builder_array_muxed0 <= main_serv_ibus_adr; end default: begin builder_array_muxed0 <= main_serv_dbus_adr; end endcase end always @(*) begin builder_array_muxed1 <= 32'd0; case (builder_grant) 1'd0: begin builder_array_muxed1 <= main_serv_ibus_dat_w; end default: begin builder_array_muxed1 <= main_serv_dbus_dat_w; end endcase end always @(*) begin builder_array_muxed2 <= 4'd0; case (builder_grant) 1'd0: begin builder_array_muxed2 <= main_serv_ibus_sel; end default: begin builder_array_muxed2 <= main_serv_dbus_sel; end endcase end always @(*) begin builder_array_muxed3 <= 1'd0; case (builder_grant) 1'd0: begin builder_array_muxed3 <= main_serv_ibus_cyc; end default: begin builder_array_muxed3 <= main_serv_dbus_cyc; end endcase end always @(*) begin builder_array_muxed4 <= 1'd0; case (builder_grant) 1'd0: begin builder_array_muxed4 <= main_serv_ibus_stb; end default: begin builder_array_muxed4 <= main_serv_dbus_stb; end endcase end always @(*) begin builder_array_muxed5 <= 1'd0; case (builder_grant) 1'd0: begin builder_array_muxed5 <= main_serv_ibus_we; end default: begin builder_array_muxed5 <= main_serv_dbus_we; end endcase end always @(*) begin builder_array_muxed6 <= 3'd0; case (builder_grant) 1'd0: begin builder_array_muxed6 <= main_serv_ibus_cti; end default: begin builder_array_muxed6 <= main_serv_dbus_cti; end endcase end always @(*) begin builder_array_muxed7 <= 2'd0; case (builder_grant) 1'd0: begin builder_array_muxed7 <= main_serv_ibus_bte; end default: begin builder_array_muxed7 <= main_serv_dbus_bte; end endcase end assign main_rx_rx = builder_impl_regs1; always @(posedge por_clk) begin if ((~main_por_done)) begin main_por_count <= (main_por_count - 1'd1); end end always @(posedge sys_clk) begin if ((main_bus_errors != 32'd4294967295)) begin if (main_bus_error) begin main_bus_errors <= (main_bus_errors + 1'd1); end end {main_tx_tick, main_tx_phase} <= 25'd20615843; if (main_tx_enable) begin {main_tx_tick, main_tx_phase} <= (main_tx_phase + 25'd20615843); end builder_rs232phytx_state <= builder_rs232phytx_next_state; if (main_tx_count_rs232phytx_next_value_ce0) begin main_tx_count <= main_tx_count_rs232phytx_next_value0; end if (main_serial_tx_rs232phytx_next_value_ce1) begin serial_tx <= main_serial_tx_rs232phytx_next_value1; end if (main_tx_data_rs232phytx_next_value_ce2) begin main_tx_data <= main_tx_data_rs232phytx_next_value2; end main_rx_rx_d <= main_rx_rx; {main_rx_tick, main_rx_phase} <= 32'd2147483648; if (main_rx_enable) begin {main_rx_tick, main_rx_phase} <= (main_rx_phase + 25'd20615843); end builder_rs232phyrx_state <= builder_rs232phyrx_next_state; if (main_rx_count_rs232phyrx_next_value_ce0) begin main_rx_count <= main_rx_count_rs232phyrx_next_value0; end if (main_rx_data_rs232phyrx_next_value_ce1) begin main_rx_data <= main_rx_data_rs232phyrx_next_value1; end if (main_uart_tx_clear) begin main_uart_tx_pending <= 1'd0; end main_uart_tx_trigger_d <= main_uart_tx_trigger; if ((main_uart_tx_trigger & (~main_uart_tx_trigger_d))) begin main_uart_tx_pending <= 1'd1; end if (main_uart_rx_clear) begin main_uart_rx_pending <= 1'd0; end main_uart_rx_trigger_d <= main_uart_rx_trigger; if ((main_uart_rx_trigger & (~main_uart_rx_trigger_d))) begin main_uart_rx_pending <= 1'd1; end if (main_uart_tx_fifo_syncfifo_re) begin main_uart_tx_fifo_readable <= 1'd1; end else begin if (main_uart_tx_fifo_re) begin main_uart_tx_fifo_readable <= 1'd0; end end if (((main_uart_tx_fifo_syncfifo_we & main_uart_tx_fifo_syncfifo_writable) & (~main_uart_tx_fifo_replace))) begin main_uart_tx_fifo_produce <= (main_uart_tx_fifo_produce + 1'd1); end if (main_uart_tx_fifo_do_read) begin main_uart_tx_fifo_consume <= (main_uart_tx_fifo_consume + 1'd1); end if (((main_uart_tx_fifo_syncfifo_we & main_uart_tx_fifo_syncfifo_writable) & (~main_uart_tx_fifo_replace))) begin if ((~main_uart_tx_fifo_do_read)) begin main_uart_tx_fifo_level0 <= (main_uart_tx_fifo_level0 + 1'd1); end end else begin if (main_uart_tx_fifo_do_read) begin main_uart_tx_fifo_level0 <= (main_uart_tx_fifo_level0 - 1'd1); end end if (main_uart_rx_fifo_syncfifo_re) begin main_uart_rx_fifo_readable <= 1'd1; end else begin if (main_uart_rx_fifo_re) begin main_uart_rx_fifo_readable <= 1'd0; end end if (((main_uart_rx_fifo_syncfifo_we & main_uart_rx_fifo_syncfifo_writable) & (~main_uart_rx_fifo_replace))) begin main_uart_rx_fifo_produce <= (main_uart_rx_fifo_produce + 1'd1); end if (main_uart_rx_fifo_do_read) begin main_uart_rx_fifo_consume <= (main_uart_rx_fifo_consume + 1'd1); end if (((main_uart_rx_fifo_syncfifo_we & main_uart_rx_fifo_syncfifo_writable) & (~main_uart_rx_fifo_replace))) begin if ((~main_uart_rx_fifo_do_read)) begin main_uart_rx_fifo_level0 <= (main_uart_rx_fifo_level0 + 1'd1); end end else begin if (main_uart_rx_fifo_do_read) begin main_uart_rx_fifo_level0 <= (main_uart_rx_fifo_level0 - 1'd1); end end if (main_timer_en_storage) begin if ((main_timer_value == 1'd0)) begin main_timer_value <= main_timer_reload_storage; end else begin main_timer_value <= (main_timer_value - 1'd1); end end else begin main_timer_value <= main_timer_load_storage; end if (main_timer_update_value_re) begin main_timer_value_status <= main_timer_value; end if (main_timer_zero_clear) begin main_timer_zero_pending <= 1'd0; end main_timer_zero_trigger_d <= main_timer_zero_trigger; if ((main_timer_zero_trigger & (~main_timer_zero_trigger_d))) begin main_timer_zero_pending <= 1'd1; end main_bus_ack <= ((main_bus_stb & main_bus_cyc) & (~main_bus_ack)); if (main_litespisdrphycore_sr_out_load) begin main_litespisdrphycore_sr_out <= (main_litespisdrphycore_sink_payload_data <<< (6'd32 - main_litespisdrphycore_sink_payload_len)); end if (main_litespisdrphycore_sr_out_shift) begin case (main_litespisdrphycore_sink_payload_width) 1'd1: begin main_litespisdrphycore_sr_out <= {main_litespisdrphycore_sr_out, main_litespisdrphycore0}; end 2'd2: begin main_litespisdrphycore_sr_out <= {main_litespisdrphycore_sr_out, main_litespisdrphycore1}; end 3'd4: begin main_litespisdrphycore_sr_out <= {main_litespisdrphycore_sr_out, main_litespisdrphycore2}; end 4'd8: begin main_litespisdrphycore_sr_out <= {main_litespisdrphycore_sr_out, main_litespisdrphycore3}; end endcase end if (main_litespisdrphycore_sr_in_shift) begin case (main_litespisdrphycore_sink_payload_width) 1'd1: begin main_litespisdrphycore_sr_in <= {main_litespisdrphycore_sr_in, main_litespisdrphycore_dq_i}; end 2'd2: begin main_litespisdrphycore_sr_in <= {main_litespisdrphycore_sr_in, main_litespisdrphycore_dq_i}; end 3'd4: begin main_litespisdrphycore_sr_in <= {main_litespisdrphycore_sr_in, main_litespisdrphycore_dq_i}; end 4'd8: begin main_litespisdrphycore_sr_in <= {main_litespisdrphycore_sr_in, main_litespisdrphycore_dq_i}; end endcase end main_litespisdrphycore_posedge_reg <= main_litespisdrphycore_posedge; main_litespisdrphycore_posedge_reg2 <= main_litespisdrphycore_posedge_reg; if ((main_litespisdrphycore_en | main_litespisdrphycore_en_int)) begin if ((main_litespisdrphycore_cnt < main_litespisdrphycore_div)) begin main_litespisdrphycore_cnt <= (main_litespisdrphycore_cnt + 1'd1); end else begin main_litespisdrphycore_cnt <= 1'd0; main_litespisdrphycore_clk <= (~main_litespisdrphycore_clk); end end else begin main_litespisdrphycore_clk <= 1'd0; main_litespisdrphycore_cnt <= 1'd0; end if (main_litespisdrphycore_wait) begin if ((~main_litespisdrphycore_done)) begin main_litespisdrphycore_count <= (main_litespisdrphycore_count - 1'd1); end end else begin main_litespisdrphycore_count <= 4'd11; end builder_litespiphy_state <= builder_litespiphy_next_state; if (main_litespisdrphycore_sr_cnt_litespiphy_next_value_ce) begin main_litespisdrphycore_sr_cnt <= main_litespisdrphycore_sr_cnt_litespiphy_next_value; end if (main_litespimmap_wait) begin if ((~main_litespimmap_done)) begin main_litespimmap_count <= (main_litespimmap_count - 1'd1); end end else begin main_litespimmap_count <= 9'd256; end builder_litespi_state <= builder_litespi_next_state; if (main_litespimmap_burst_cs_litespi_next_value_ce0) begin main_litespimmap_burst_cs <= main_litespimmap_burst_cs_litespi_next_value0; end if (main_litespimmap_burst_adr_litespi_next_value_ce1) begin main_litespimmap_burst_adr <= main_litespimmap_burst_adr_litespi_next_value1; end if (main_done) begin main_chaser <= {main_chaser, (~main_chaser[4])}; end if (main_re) begin main_mode <= 1'd1; end if (main_wait) begin if ((~main_done)) begin main_count <= (main_count - 1'd1); end end else begin main_count <= 22'd2400000; end builder_state <= builder_next_state; case (builder_grant) 1'd0: begin if ((~builder_request[0])) begin if (builder_request[1]) begin builder_grant <= 1'd1; end end end 1'd1: begin if ((~builder_request[1])) begin if (builder_request[0]) begin builder_grant <= 1'd0; end end end endcase builder_slave_sel_r <= builder_slave_sel; if (builder_wait) begin if ((~builder_done)) begin builder_count <= (builder_count - 1'd1); end end else begin builder_count <= 20'd1000000; end builder_csr_bankarray_interface0_bank_bus_dat_r <= 1'd0; if (builder_csr_bankarray_csrbank0_sel) begin case (builder_csr_bankarray_interface0_bank_bus_adr[8:0]) 1'd0: begin builder_csr_bankarray_interface0_bank_bus_dat_r <= builder_csr_bankarray_csrbank0_reset0_w; end 1'd1: begin builder_csr_bankarray_interface0_bank_bus_dat_r <= builder_csr_bankarray_csrbank0_scratch0_w; end 2'd2: begin builder_csr_bankarray_interface0_bank_bus_dat_r <= builder_csr_bankarray_csrbank0_bus_errors_w; end endcase end if (builder_csr_bankarray_csrbank0_reset0_re) begin main_reset_storage[1:0] <= builder_csr_bankarray_csrbank0_reset0_r; end main_reset_re <= builder_csr_bankarray_csrbank0_reset0_re; if (builder_csr_bankarray_csrbank0_scratch0_re) begin main_scratch_storage[31:0] <= builder_csr_bankarray_csrbank0_scratch0_r; end main_scratch_re <= builder_csr_bankarray_csrbank0_scratch0_re; main_bus_errors_re <= builder_csr_bankarray_csrbank0_bus_errors_re; builder_csr_bankarray_sel_r <= builder_csr_bankarray_sel; builder_csr_bankarray_interface1_bank_bus_dat_r <= 1'd0; if (builder_csr_bankarray_csrbank1_sel) begin case (builder_csr_bankarray_interface1_bank_bus_adr[8:0]) 1'd0: begin builder_csr_bankarray_interface1_bank_bus_dat_r <= builder_csr_bankarray_csrbank1_out0_w; end endcase end if (builder_csr_bankarray_csrbank1_out0_re) begin main_storage[4:0] <= builder_csr_bankarray_csrbank1_out0_r; end main_re <= builder_csr_bankarray_csrbank1_out0_re; builder_csr_bankarray_interface2_bank_bus_dat_r <= 1'd0; if (builder_csr_bankarray_csrbank2_sel) begin case (builder_csr_bankarray_interface2_bank_bus_adr[8:0]) 1'd0: begin builder_csr_bankarray_interface2_bank_bus_dat_r <= builder_csr_bankarray_csrbank2_mmap_dummy_bits0_w; end endcase end if (builder_csr_bankarray_csrbank2_mmap_dummy_bits0_re) begin main_litespimmap_storage[7:0] <= builder_csr_bankarray_csrbank2_mmap_dummy_bits0_r; end main_litespimmap_re <= builder_csr_bankarray_csrbank2_mmap_dummy_bits0_re; builder_csr_bankarray_interface3_bank_bus_dat_r <= 1'd0; if (builder_csr_bankarray_csrbank3_sel) begin case (builder_csr_bankarray_interface3_bank_bus_adr[8:0]) 1'd0: begin builder_csr_bankarray_interface3_bank_bus_dat_r <= builder_csr_bankarray_csrbank3_clk_divisor0_w; end endcase end if (builder_csr_bankarray_csrbank3_clk_divisor0_re) begin main_litespisdrphycore_storage[7:0] <= builder_csr_bankarray_csrbank3_clk_divisor0_r; end main_litespisdrphycore_re <= builder_csr_bankarray_csrbank3_clk_divisor0_re; builder_csr_bankarray_interface4_bank_bus_dat_r <= 1'd0; if (builder_csr_bankarray_csrbank4_sel) begin case (builder_csr_bankarray_interface4_bank_bus_adr[8:0]) 1'd0: begin builder_csr_bankarray_interface4_bank_bus_dat_r <= builder_csr_bankarray_csrbank4_load0_w; end 1'd1: begin builder_csr_bankarray_interface4_bank_bus_dat_r <= builder_csr_bankarray_csrbank4_reload0_w; end 2'd2: begin builder_csr_bankarray_interface4_bank_bus_dat_r <= builder_csr_bankarray_csrbank4_en0_w; end 2'd3: begin builder_csr_bankarray_interface4_bank_bus_dat_r <= builder_csr_bankarray_csrbank4_update_value0_w; end 3'd4: begin builder_csr_bankarray_interface4_bank_bus_dat_r <= builder_csr_bankarray_csrbank4_value_w; end 3'd5: begin builder_csr_bankarray_interface4_bank_bus_dat_r <= builder_csr_bankarray_csrbank4_ev_status_w; end 3'd6: begin builder_csr_bankarray_interface4_bank_bus_dat_r <= builder_csr_bankarray_csrbank4_ev_pending_w; end 3'd7: begin builder_csr_bankarray_interface4_bank_bus_dat_r <= builder_csr_bankarray_csrbank4_ev_enable0_w; end endcase end if (builder_csr_bankarray_csrbank4_load0_re) begin main_timer_load_storage[31:0] <= builder_csr_bankarray_csrbank4_load0_r; end main_timer_load_re <= builder_csr_bankarray_csrbank4_load0_re; if (builder_csr_bankarray_csrbank4_reload0_re) begin main_timer_reload_storage[31:0] <= builder_csr_bankarray_csrbank4_reload0_r; end main_timer_reload_re <= builder_csr_bankarray_csrbank4_reload0_re; if (builder_csr_bankarray_csrbank4_en0_re) begin main_timer_en_storage <= builder_csr_bankarray_csrbank4_en0_r; end main_timer_en_re <= builder_csr_bankarray_csrbank4_en0_re; if (builder_csr_bankarray_csrbank4_update_value0_re) begin main_timer_update_value_storage <= builder_csr_bankarray_csrbank4_update_value0_r; end main_timer_update_value_re <= builder_csr_bankarray_csrbank4_update_value0_re; main_timer_value_re <= builder_csr_bankarray_csrbank4_value_re; main_timer_status_re <= builder_csr_bankarray_csrbank4_ev_status_re; if (builder_csr_bankarray_csrbank4_ev_pending_re) begin main_timer_pending_r <= builder_csr_bankarray_csrbank4_ev_pending_r; end main_timer_pending_re <= builder_csr_bankarray_csrbank4_ev_pending_re; if (builder_csr_bankarray_csrbank4_ev_enable0_re) begin main_timer_enable_storage <= builder_csr_bankarray_csrbank4_ev_enable0_r; end main_timer_enable_re <= builder_csr_bankarray_csrbank4_ev_enable0_re; builder_csr_bankarray_interface5_bank_bus_dat_r <= 1'd0; if (builder_csr_bankarray_csrbank5_sel) begin case (builder_csr_bankarray_interface5_bank_bus_adr[8:0]) 1'd0: begin builder_csr_bankarray_interface5_bank_bus_dat_r <= main_uart_rxtx_w; end 1'd1: begin builder_csr_bankarray_interface5_bank_bus_dat_r <= builder_csr_bankarray_csrbank5_txfull_w; end 2'd2: begin builder_csr_bankarray_interface5_bank_bus_dat_r <= builder_csr_bankarray_csrbank5_rxempty_w; end 2'd3: begin builder_csr_bankarray_interface5_bank_bus_dat_r <= builder_csr_bankarray_csrbank5_ev_status_w; end 3'd4: begin builder_csr_bankarray_interface5_bank_bus_dat_r <= builder_csr_bankarray_csrbank5_ev_pending_w; end 3'd5: begin builder_csr_bankarray_interface5_bank_bus_dat_r <= builder_csr_bankarray_csrbank5_ev_enable0_w; end 3'd6: begin builder_csr_bankarray_interface5_bank_bus_dat_r <= builder_csr_bankarray_csrbank5_txempty_w; end 3'd7: begin builder_csr_bankarray_interface5_bank_bus_dat_r <= builder_csr_bankarray_csrbank5_rxfull_w; end endcase end main_uart_txfull_re <= builder_csr_bankarray_csrbank5_txfull_re; main_uart_rxempty_re <= builder_csr_bankarray_csrbank5_rxempty_re; main_uart_status_re <= builder_csr_bankarray_csrbank5_ev_status_re; if (builder_csr_bankarray_csrbank5_ev_pending_re) begin main_uart_pending_r[1:0] <= builder_csr_bankarray_csrbank5_ev_pending_r; end main_uart_pending_re <= builder_csr_bankarray_csrbank5_ev_pending_re; if (builder_csr_bankarray_csrbank5_ev_enable0_re) begin main_uart_enable_storage[1:0] <= builder_csr_bankarray_csrbank5_ev_enable0_r; end main_uart_enable_re <= builder_csr_bankarray_csrbank5_ev_enable0_re; main_uart_txempty_re <= builder_csr_bankarray_csrbank5_txempty_re; main_uart_rxfull_re <= builder_csr_bankarray_csrbank5_rxfull_re; if (sys_rst) begin main_reset_storage <= 2'd0; main_reset_re <= 1'd0; main_scratch_storage <= 32'd305419896; main_scratch_re <= 1'd0; main_bus_errors_re <= 1'd0; main_bus_errors <= 32'd0; serial_tx <= 1'd1; main_tx_tick <= 1'd0; main_rx_tick <= 1'd0; main_rx_rx_d <= 1'd0; main_uart_txfull_re <= 1'd0; main_uart_rxempty_re <= 1'd0; main_uart_tx_pending <= 1'd0; main_uart_tx_trigger_d <= 1'd0; main_uart_rx_pending <= 1'd0; main_uart_rx_trigger_d <= 1'd0; main_uart_status_re <= 1'd0; main_uart_pending_re <= 1'd0; main_uart_pending_r <= 2'd0; main_uart_enable_storage <= 2'd0; main_uart_enable_re <= 1'd0; main_uart_txempty_re <= 1'd0; main_uart_rxfull_re <= 1'd0; main_uart_tx_fifo_readable <= 1'd0; main_uart_tx_fifo_level0 <= 5'd0; main_uart_tx_fifo_produce <= 4'd0; main_uart_tx_fifo_consume <= 4'd0; main_uart_rx_fifo_readable <= 1'd0; main_uart_rx_fifo_level0 <= 5'd0; main_uart_rx_fifo_produce <= 4'd0; main_uart_rx_fifo_consume <= 4'd0; main_timer_load_storage <= 32'd0; main_timer_load_re <= 1'd0; main_timer_reload_storage <= 32'd0; main_timer_reload_re <= 1'd0; main_timer_en_storage <= 1'd0; main_timer_en_re <= 1'd0; main_timer_update_value_storage <= 1'd0; main_timer_update_value_re <= 1'd0; main_timer_value_status <= 32'd0; main_timer_value_re <= 1'd0; main_timer_zero_pending <= 1'd0; main_timer_zero_trigger_d <= 1'd0; main_timer_status_re <= 1'd0; main_timer_pending_re <= 1'd0; main_timer_pending_r <= 1'd0; main_timer_enable_storage <= 1'd0; main_timer_enable_re <= 1'd0; main_timer_value <= 32'd0; main_bus_ack <= 1'd0; main_litespisdrphycore_storage <= 8'd1; main_litespisdrphycore_re <= 1'd0; main_litespisdrphycore_cnt <= 8'd0; main_litespisdrphycore_clk <= 1'd0; main_litespisdrphycore_posedge_reg <= 1'd0; main_litespisdrphycore_posedge_reg2 <= 1'd0; main_litespisdrphycore_count <= 4'd11; main_litespimmap_burst_cs <= 1'd0; main_litespimmap_count <= 9'd256; main_litespimmap_storage <= 8'd0; main_litespimmap_re <= 1'd0; main_storage <= 5'd0; main_re <= 1'd0; main_chaser <= 5'd0; main_mode <= 1'd0; main_count <= 22'd2400000; builder_rs232phytx_state <= 1'd0; builder_rs232phyrx_state <= 1'd0; builder_litespiphy_state <= 2'd0; builder_litespi_state <= 4'd0; builder_grant <= 1'd0; builder_slave_sel_r <= 3'd0; builder_count <= 20'd1000000; builder_csr_bankarray_sel_r <= 1'd0; builder_state <= 1'd0; end builder_impl_regs0 <= serial_rx; builder_impl_regs1 <= builder_impl_regs0; end reg [7:0] mem[0:43]; reg [5:0] memadr; always @(posedge sys_clk) begin memadr <= builder_csr_bankarray_adr; end assign builder_csr_bankarray_dat_r = mem[memadr]; initial begin $readmemh("mem.init", mem); end reg [9:0] storage[0:15]; reg [9:0] memdat; reg [9:0] memdat_1; always @(posedge sys_clk) begin if (main_uart_tx_fifo_wrport_we) storage[main_uart_tx_fifo_wrport_adr] <= main_uart_tx_fifo_wrport_dat_w; memdat <= storage[main_uart_tx_fifo_wrport_adr]; end always @(posedge sys_clk) begin if (main_uart_tx_fifo_rdport_re) memdat_1 <= storage[main_uart_tx_fifo_rdport_adr]; end assign main_uart_tx_fifo_wrport_dat_r = memdat; assign main_uart_tx_fifo_rdport_dat_r = memdat_1; reg [9:0] storage_1[0:15]; reg [9:0] memdat_2; reg [9:0] memdat_3; always @(posedge sys_clk) begin if (main_uart_rx_fifo_wrport_we) storage_1[main_uart_rx_fifo_wrport_adr] <= main_uart_rx_fifo_wrport_dat_w; memdat_2 <= storage_1[main_uart_rx_fifo_wrport_adr]; end always @(posedge sys_clk) begin if (main_uart_rx_fifo_rdport_re) memdat_3 <= storage_1[main_uart_rx_fifo_rdport_adr]; end assign main_uart_rx_fifo_wrport_dat_r = memdat_2; assign main_uart_rx_fifo_rdport_dat_r = memdat_3; SB_SPRAM256KA SB_SPRAM256KA( .ADDRESS(main_bus_adr[13:0]), .CHIPSELECT(1'd1), .CLOCK(sys_clk), .DATAIN(main_datain0), .MASKWREN(main_maskwren0), .POWEROFF(1'd1), .SLEEP(1'd0), .STANDBY(1'd0), .WREN(main_wren0), .DATAOUT(main_dataout0) ); SB_SPRAM256KA SB_SPRAM256KA_1( .ADDRESS(main_bus_adr[13:0]), .CHIPSELECT(1'd1), .CLOCK(sys_clk), .DATAIN(main_datain1), .MASKWREN(main_maskwren1), .POWEROFF(1'd1), .SLEEP(1'd0), .STANDBY(1'd0), .WREN(main_wren1), .DATAOUT(main_dataout1) ); SB_SPRAM256KA SB_SPRAM256KA_2( .ADDRESS(main_bus_adr[13:0]), .CHIPSELECT(1'd1), .CLOCK(sys_clk), .DATAIN(main_datain2), .MASKWREN(main_maskwren2), .POWEROFF(1'd1), .SLEEP(1'd0), .STANDBY(1'd0), .WREN(main_wren2), .DATAOUT(main_dataout2) ); SB_SPRAM256KA SB_SPRAM256KA_3( .ADDRESS(main_bus_adr[13:0]), .CHIPSELECT(1'd1), .CLOCK(sys_clk), .DATAIN(main_datain3), .MASKWREN(main_maskwren3), .POWEROFF(1'd1), .SLEEP(1'd0), .STANDBY(1'd0), .WREN(main_wren3), .DATAOUT(main_dataout3) ); serv_rf_top #( .RESET_PC(32'd2147745792) ) serv_rf_top ( .clk(sys_clk), .i_dbus_ack(main_serv_dbus_ack), .i_dbus_rdt(main_serv_dbus_dat_r), .i_ibus_ack(main_serv_ibus_ack), .i_ibus_rdt(main_serv_ibus_dat_r), .i_rst((sys_rst | main_serv_reset)), .i_timer_irq(1'd0), .o_dbus_adr({main_serv_dbus_adr, main_serv1}), .o_dbus_cyc(main_serv_dbus_cyc), .o_dbus_dat(main_serv_dbus_dat_w), .o_dbus_sel(main_serv_dbus_sel), .o_dbus_we(main_serv_dbus_we), .o_ibus_adr({main_serv_ibus_adr, main_serv0}), .o_ibus_cyc(main_serv_ibus_cyc) ); SB_PLL40_PAD #( .DIVF(6'd63), .DIVQ(3'd5), .DIVR(1'd0), .FEEDBACK_PATH("SIMPLE"), .FILTER_RANGE(1'd1) ) SB_PLL40_PAD ( .PACKAGEPIN(main_clkin), .RESETB((~main_reset)), .LOCK(main_locked), .PLLOUTGLOBAL(main_clkout) ); SB_DFFS SB_DFFS( .C(sys_clk), .D(1'd0), .S(((~main_por_done) | (~main_locked))), .Q(builder_impl_rst1) ); SB_DFFS SB_DFFS_1( .C(sys_clk), .D(builder_impl_rst1), .S(((~main_por_done) | (~main_locked))), .Q(sys_rst) ); SB_IO #( .IO_STANDARD("SB_LVCMOS"), .PIN_TYPE(6'd20) ) SB_IO ( .CLOCK_ENABLE(1'd1), .D_OUT_0(main_litespisdrphycore_clk), .OUTPUT_CLK(sys_clk), .OUTPUT_ENABLE(1'd1), .PACKAGE_PIN(spiflash_clk) ); SB_IO #( .IO_STANDARD("SB_LVCMOS"), .PIN_TYPE(6'd20) ) SB_IO_1 ( .CLOCK_ENABLE(1'd1), .D_OUT_0(main_litespisdrphycore_dq_o), .OUTPUT_CLK(sys_clk), .OUTPUT_ENABLE(1'd1), .PACKAGE_PIN(spiflash_mosi) ); SB_IO #( .IO_STANDARD("SB_LVCMOS"), .PIN_TYPE(6'd0) ) SB_IO_2 ( .CLOCK_ENABLE(1'd1), .INPUT_CLK(sys_clk), .PACKAGE_PIN(spiflash_miso), .D_IN_0(main_litespisdrphycore_dq_i), .D_IN_1(builder_impl) ); endmodule